cd04a5f1aa
The current code assumed that READ/WRITE would produce atomic read/writes for 8/16/32-bit words, which in turned put assumption on the memcpy function. Since some memcpy implementation do not always guarantee such strong assumption, introduce two new operation READ/WRITE_ATOMIC which provide the necessary tools to do correct read and write to register in a single memory access. Change-Id: I37451bd5057bb0dcaf5a800d8aef8791c792a090
61 lines
1.7 KiB
ArmAsm
61 lines
1.7 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2014 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "mips.h"
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.set noreorder
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.section .text, "ax", %progbits
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.global target_read8
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.type target_read8, %function
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.global target_read16
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.type target_read16, %function
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.global target_read32
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.type target_read32, %function
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.global target_write8
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.type target_write8, %function
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.global target_write16
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.type target_write16, %function
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.global target_write32
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.type target_write32, %function
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target_read8:
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jr ra
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lbu v0, 0(a0)
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target_read16:
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jr ra
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lhu v0, 0(a0)
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target_read32:
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jr ra
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lw v0, 0(a0)
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target_write8:
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jr ra
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sb a1, 0(a0)
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target_write16:
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jr ra
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sh a1, 0(a0)
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target_write32:
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jr ra
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sw a1, 0(a0)
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.set reorder
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