6f40387e74
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28952 a1c6a512-1295-4272-9138-f99709370657
132 lines
4 KiB
C
132 lines
4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "kernel.h"
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#include "thread.h"
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#include "system.h"
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#include "dma-target.h"
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#include "dm320.h"
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#include "ata.h"
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#include "ata-target.h"
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#include "ata-defines.h"
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#include <stdbool.h>
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#define CS1_START 0x50000000
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#define CS2_START 0x60000000
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#define SDRAM_START 0x00900000
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#define FLASH_START 0x00100000
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#define CF_START 0x40000000
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#define SSFDC_START 0x48000000
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static struct wakeup transfer_completion_signal;
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static bool dma_in_progress = false;
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void MTC0(void)
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{
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IO_INTC_IRQ1 = INTR_IRQ1_MTC0;
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wakeup_signal(&transfer_completion_signal);
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dma_in_progress = false;
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}
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void dma_start(const void* addr, size_t size)
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{
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/* Compatibility with Gigabeat S in dma_start.c */
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(void) addr;
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(void) size;
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}
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#define ATA_DEST (ATA_IOBASE-CS1_START)
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void dma_ata_read(unsigned char* buf, int shortcount)
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{
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if(dma_in_progress)
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wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
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while((unsigned long)buf & 0x1F)
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{
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unsigned short tmp;
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tmp = ATA_IN16(ATA_DATA);
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*buf++ = tmp & 0xFF;
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*buf++ = tmp >> 8;
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shortcount--;
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}
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if (!shortcount)
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return;
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IO_SDRAM_SDDMASEL = 0x0820; /* 32-byte burst mode transfer */
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IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
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IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & 0x7FFF; /* Set variable address */
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IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF;
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IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */
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IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF;
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IO_EMIF_DMASIZE = shortcount/2; /* 16-bits *2 = 1 word */
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IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */
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dma_in_progress = true;
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wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
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if(shortcount % 2)
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{
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unsigned short tmp;
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tmp = ATA_IN16(ATA_DATA);
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*buf++ = tmp & 0xFF;
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*buf++ = tmp >> 8;
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}
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}
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void dma_ata_write(unsigned char* buf, int wordcount)
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{
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if(dma_in_progress)
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wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
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while((unsigned long)buf & 0x1F)
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{
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unsigned short tmp;
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tmp = (unsigned short) *buf++;
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tmp |= (unsigned short) *buf++ << 8;
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ATA_OUT16(ATA_DATA, tmp);
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wordcount--;
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}
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if (!wordcount)
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return;
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IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */
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IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */
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IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & ~(1 << 15); /* Set variable address */
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IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF;
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IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */
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IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF;
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IO_EMIF_DMASIZE = (wordcount+1)/2;
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IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */
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dma_in_progress = true;
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wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
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}
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void dma_init(void)
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{
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IO_INTC_EINT1 |= INTR_EINT1_MTC0; /* enable MTC interrupt */
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wakeup_init(&transfer_completion_signal);
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dma_in_progress = false;
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}
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