7abf2b53a4
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657
212 lines
6.6 KiB
C
212 lines
6.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdio.h>
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#include "system.h"
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#include "imx31l.h"
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#include "avic-imx31.h"
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#include "panic.h"
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#include "debug.h"
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static const char * avic_int_names[64] =
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{
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"RESERVED0", "RESERVED1", "RESERVED2", "I2C3",
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"I2C2", "MPEG4_ENCODER", "RTIC", "FIR",
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"MMC/SDHC2", "MMC/SDHC1", "I2C1", "SSI2",
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"SSI1", "CSPI2", "CSPI1", "ATA",
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"MBX", "CSPI3", "UART3", "IIM",
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"SIM1", "SIM2", "RNGA", "EVTMON",
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"KPP", "RTC", "PWN", "EPIT2",
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"EPIT1", "GPT", "PWR_FAIL", "CCM_DVFS",
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"UART2", "NANDFC", "SDMA", "USB_HOST1",
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"USB_HOST2", "USB_OTG", "RESERVED3", "MSHC1",
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"MSHC2", "IPU_ERR", "IPU", "RESERVED4",
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"RESERVED5", "UART1", "UART4", "UART5",
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"ETC_IRQ", "SCC_SCM", "SCC_SMN", "GPIO2",
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"GPIO1", "CCM_CLK", "PCMCIA", "WDOG",
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"GPIO3", "RESERVED6", "EXT_PWMG", "EXT_TEMP",
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"EXT_SENS1", "EXT_SENS2", "EXT_WDOG", "EXT_TV"
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};
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void UIE_VECTOR(void)
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{
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int mode;
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int offset;
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asm volatile (
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"mrs %0, cpsr \n" /* Mask core IRQ/FIQ */
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"orr %0, %0, #0xc0 \n"
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"msr cpsr_c, %0 \n"
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"and %0, %0, #0x1f \n" /* Get mode bits */
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: "=&r"(mode)
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);
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offset = mode == 0x11 ?
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(int32_t)AVIC_FIVECSR : ((int32_t)AVIC_NIVECSR >> 16);
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panicf("Unhandled %s %d: %s",
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mode == 0x11 ? "FIQ" : "IRQ", offset,
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offset >= 0 ? avic_int_names[offset] : "<Unknown>");
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}
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/* We use the AVIC */
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void __attribute__((interrupt("IRQ"))) irq_handler(void)
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{
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const int offset = (int32_t)AVIC_NIVECSR >> 16;
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if (offset == -1)
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{
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/* This is called occasionally for some unknown reason even with the
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* avic enabled but returning normally appears to cause no harm. The
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* KPP and ATA seem to have a part in it (common but multiplexed pins
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* that can interfere). It will be investigated more thoroughly but
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* for now it is simply an occasional irritant. */
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return;
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}
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disable_interrupt(IRQ_FIQ_STATUS);
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panicf("Unhandled IRQ %d in irq_handler: %s", offset,
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offset >= 0 ? avic_int_names[offset] : "<Unknown>");
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}
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/* Accoring to section 9.3.5 of the UM, the AVIC doesn't accelerate
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* fast interrupts and they must be dispatched */
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void __attribute__((naked)) fiq_handler(void)
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{
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asm volatile (
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"mov r10, #0x68000000 \n" /* load AVIC base address */
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"ldr r9, [r10, #0x44] \n" /* read FIVECSR of AVIC */
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"add r10, r10, #0x100 \n" /* move pointer to base of VECTOR table */
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"ldr r8, [r10, r9, lsl #2] \n" /* read FIQ vector from VECTOR table */
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"bx r8 \n" /* jump to FIQ service routine */
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);
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}
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void avic_init(void)
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{
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struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
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int i;
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/* Disable all interrupts and set to unhandled */
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avic_disable_int(INT_ALL);
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/* Reset AVIC control */
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avic->intcntl = 0;
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/* Init all interrupts to type IRQ */
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avic_set_int_type(INT_ALL, INT_TYPE_IRQ);
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/* Set all normal to lowest priority */
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for (i = 0; i < 8; i++)
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avic->nipriority[i] = 0;
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/* Set NM bit to enable VIC */
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avic->intcntl |= AVIC_INTCNTL_NM;
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/* Enable VE bit in CP15 Control reg to enable VIC */
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asm volatile (
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"mrc p15, 0, r0, c1, c0, 0 \n"
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"orr r0, r0, #(1 << 24) \n"
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"mcr p15, 0, r0, c1, c0, 0 \n"
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: : : "r0");
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/* Enable normal interrupts at all priorities */
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avic->nimask = 0x1f;
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}
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void avic_set_int_priority(enum IMX31_INT_LIST ints,
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unsigned long ni_priority)
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{
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struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
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volatile uint32_t *reg = &avic->nipriority[7 - (ints >> 3)];
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unsigned int shift = (ints & 0x7) << 2;
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uint32_t mask = 0xful << shift;
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*reg = (*reg & ~mask) | ((ni_priority << shift) & mask);
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}
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void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype,
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unsigned long ni_priority, void (*handler)(void))
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{
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struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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if (ints != INT_ALL) /* No mass-enable allowed */
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{
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avic_set_int_type(ints, intstype);
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avic->vector[ints] = (long)handler;
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avic->intennum = ints;
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avic_set_int_priority(ints, ni_priority);
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}
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restore_interrupt(oldstatus);
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}
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void avic_disable_int(enum IMX31_INT_LIST ints)
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{
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struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
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uint32_t i;
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if (ints == INT_ALL)
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{
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for (i = 0; i < 64; i++)
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{
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avic->intdisnum = i;
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avic->vector[i] = (long)UIE_VECTOR;
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}
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}
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else
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{
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avic->intdisnum = ints;
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avic->vector[ints] = (long)UIE_VECTOR;
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}
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}
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static void set_int_type(int i, enum INT_TYPE intstype)
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{
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/* INTTYPEH: vectors 63-32, INTTYPEL: vectors 31-0 */
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struct avic_map * const avic = (struct avic_map *)AVIC_BASE_ADDR;
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volatile uint32_t *reg = &avic->inttype[1 - (i >> 5)];
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uint32_t val = 1L << (i & 0x1f);
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if (intstype == INT_TYPE_IRQ)
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val = *reg & ~val;
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else
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val = *reg | val;
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*reg = val;
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}
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void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype)
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{
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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if (ints == INT_ALL)
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{
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int i;
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for (i = 0; i < 64; i++)
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set_int_type(i, intstype);
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}
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else
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{
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set_int_type(ints, intstype);
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}
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restore_interrupt(oldstatus);
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}
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