d2595ec075
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21001 a1c6a512-1295-4272-9138-f99709370657
889 lines
23 KiB
C
889 lines
23 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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//#define LOGF_ENABLE
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#include "logf.h"
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#include "system.h"
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#include "usb_ch9.h"
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#include "usb_drv.h"
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#include "usb_core.h"
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#include "usb-target.h"
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#include "jz4740.h"
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#include "thread.h"
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/*
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The Jz4740 USB controller is called MUSBHSFC in the datasheet.
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It also seems to be a more generic controller, with support for
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up to 15 endpoints (the Jz4740 only has 3).
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*/
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#define USB_EP0_IDLE 0
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#define USB_EP0_RX 1
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#define USB_EP0_TX 2
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#define EP_BUF_LEFT(ep) ((ep)->length - (ep)->sent)
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#define EP_PTR(ep) ((void*)((unsigned int)(ep)->buf + (ep)->sent))
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#define EP_NUMBER(ep) (((int)(ep) - (int)&endpoints[0])/sizeof(struct usb_endpoint))
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#define EP_NUMBER2(ep) (EP_NUMBER((ep))/2)
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#define TOTAL_EP() (sizeof(endpoints)/sizeof(struct usb_endpoint))
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#define EP_IS_IN(ep) (EP_NUMBER((ep))%2)
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enum ep_type
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{
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ep_control, ep_bulk, ep_interrupt
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};
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struct usb_endpoint
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{
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void *buf;
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unsigned int length;
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union
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{
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unsigned int sent;
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unsigned int received;
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};
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bool busy;
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const enum ep_type type;
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const bool use_dma;
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bool wait;
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const unsigned int fifo_addr;
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unsigned short fifo_size;
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};
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static unsigned char ep0_rx_buf[64];
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static unsigned char ep0state = USB_EP0_IDLE;
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static struct usb_endpoint endpoints[] =
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{
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/* buf length sent busy type use_dma wait fifo_addr fifo_size */
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{NULL, 0, {0}, false, ep_control, false, false, USB_FIFO_EP0, 64 },
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{&ep0_rx_buf, 0, {0}, false, ep_control, false, false, USB_FIFO_EP0, 64 },
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{NULL, 0, {0}, false, ep_bulk, false, false, USB_FIFO_EP1, 512},
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{NULL, 0, {0}, false, ep_bulk, false, false, USB_FIFO_EP1, 512},
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{NULL, 0, {0}, false, ep_interrupt, false, false, USB_FIFO_EP2, 64 }
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};
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static struct wakeup ep_wkup[TOTAL_EP()];
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static inline void select_endpoint(int ep)
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{
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REG_USB_REG_INDEX = ep;
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}
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static void readFIFO(struct usb_endpoint *ep, unsigned int size)
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{
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logf("readFIFO(EP%d, %d)", EP_NUMBER2(ep), size);
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register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
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register unsigned int *ptr32 = (unsigned int*)ptr;
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register unsigned int s = size >> 2;
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register unsigned int x;
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if(size > 0)
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{
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if( ((unsigned int)ptr & 3) == 0 )
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{
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while(s--)
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*ptr32++ = REG32(ep->fifo_addr);
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ptr = (unsigned char*)ptr32;
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}
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else
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{
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while(s--)
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{
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x = REG32(ep->fifo_addr);
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*ptr++ = (x >> 0) & 0xFF;
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*ptr++ = (x >> 8) & 0xFF;
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*ptr++ = (x >> 16) & 0xFF;
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*ptr++ = (x >> 24) & 0xFF;
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}
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}
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s = size & 3;
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while(s--)
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*ptr++ = REG8(ep->fifo_addr);
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}
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}
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static void writeFIFO(struct usb_endpoint *ep, unsigned int size)
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{
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logf("writeFIFO(EP%d, %d)", EP_NUMBER2(ep), size);
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register unsigned int *d32 = (unsigned int *)EP_PTR(ep);
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register unsigned char *d8 = (unsigned char *)EP_PTR(ep);
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register unsigned int s;
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if(size > 0)
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{
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if(UNLIKELY((unsigned int)d8 & 3))
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{
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s = size;
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while(s--)
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REG8(ep->fifo_addr) = *d8++;
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}
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else
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{
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s = size >> 2;
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while (s--)
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REG32(ep->fifo_addr) = *d32++;
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if( (s = size & 3) )
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{
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d8 = (unsigned char *)d32;
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while (s--)
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REG8(ep->fifo_addr) = *d8++;
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}
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}
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}
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}
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static void flushFIFO(struct usb_endpoint *ep)
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{
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logf("flushFIFO(%d)", EP_NUMBER(ep));
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switch (ep->type)
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{
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case ep_control:
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break;
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case ep_bulk:
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case ep_interrupt:
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if(EP_IS_IN(ep))
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REG_USB_REG_INCSR |= (USB_INCSR_FF | USB_INCSR_CDT);
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else
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REG_USB_REG_OUTCSR |= (USB_OUTCSR_FF | USB_OUTCSR_CDT);
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break;
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}
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}
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static void EP0_send(void)
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{
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struct usb_endpoint* ep = &endpoints[0];
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unsigned int length;
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unsigned char csr0;
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select_endpoint(0);
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csr0 = REG_USB_REG_CSR0;
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if(ep->length == 0)
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{
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//REG_USB_REG_CSR0 = (csr0 | USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND);
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REG_USB_REG_CSR0 = (csr0 | USB_CSR0_SVDOUTPKTRDY);
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return;
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}
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if(ep->sent == 0)
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length = (ep->length <= ep->fifo_size ? ep->length : ep->fifo_size);
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else
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length = (EP_BUF_LEFT(ep) <= ep->fifo_size ? EP_BUF_LEFT(ep) : ep->fifo_size);
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writeFIFO(ep, length);
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ep->sent += length;
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if(ep->sent >= ep->length)
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{
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REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY | USB_CSR0_DATAEND); /* Set data end! */
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ep0state = USB_EP0_IDLE;
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if(ep->wait)
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wakeup_signal(&ep_wkup[0]);
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}
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else
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REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY);
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}
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static void EP0_handler(void)
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{
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logf("EP0_handler");
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unsigned char csr0;
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/* Read CSR0 */
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select_endpoint(0);
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csr0 = REG_USB_REG_CSR0;
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/* Check for SentStall:
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This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
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*/
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if(csr0 & USB_CSR0_SENTSTALL)
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{
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REG_USB_REG_CSR0 = csr0 & ~USB_CSR0_SENTSTALL;
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ep0state = USB_EP0_IDLE;
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return;
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}
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/* Check for SetupEnd:
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This bit will be set when a control transaction ends before the DataEnd bit has been set.
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An interrupt will be generated and the FIFO flushed at this time.
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The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.
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*/
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if(csr0 & USB_CSR0_SETUPEND)
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{
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REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDSETUPEND;
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ep0state = USB_EP0_IDLE;
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return;
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}
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/* Call relevant routines for endpoint 0 state */
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if(ep0state == USB_EP0_IDLE)
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{
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if(csr0 & USB_CSR0_OUTPKTRDY) /* There is a packet in the fifo */
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{
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readFIFO(&endpoints[1], REG_USB_REG_COUNT0);
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REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDOUTPKTRDY; /* clear OUTPKTRDY bit */
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usb_core_control_request((struct usb_ctrlrequest*)endpoints[1].buf);
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if(endpoints[1].wait)
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wakeup_signal(&ep_wkup[1]);
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}
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}
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else if(ep0state == USB_EP0_TX)
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EP0_send();
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}
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static void EPIN_handler(unsigned int endpoint)
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{
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struct usb_endpoint* ep = &endpoints[endpoint*2];
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unsigned int length, csr;
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select_endpoint(endpoint);
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csr = REG_USB_REG_INCSR;
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logf("EPIN_handler(%d): 0x%x", endpoint, csr);
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if(!ep->busy)
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return;
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if(csr & USB_INCSR_SENTSTALL)
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{
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REG_USB_REG_INCSR = csr & ~USB_INCSR_SENTSTALL;
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return;
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}
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if(ep->use_dma)
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return;
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if(csr & USB_INCSR_FFNOTEMPT)
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{
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logf("FIFO is not empty! 0x%x", csr);
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return;
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}
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logf("EP%d: %d -> %d", endpoint, ep->sent, ep->length);
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if(ep->sent == 0)
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length = (ep->length <= ep->fifo_size ? ep->length : ep->fifo_size);
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else
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length = (EP_BUF_LEFT(ep) <= ep->fifo_size ? EP_BUF_LEFT(ep) : ep->fifo_size);
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writeFIFO(ep, length);
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REG_USB_REG_INCSR = csr | USB_INCSR_INPKTRDY;
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ep->sent += length;
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if(ep->sent >= ep->length)
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{
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usb_core_transfer_complete(endpoint, USB_DIR_IN, 0, ep->sent);
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if(ep->wait)
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wakeup_signal(&ep_wkup[endpoint*2]);
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logf("sent complete");
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ep->sent = 0;
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ep->length = 0;
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ep->buf = NULL;
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ep->busy = false;
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}
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}
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static void EPOUT_handler(unsigned int endpoint)
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{
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struct usb_endpoint* ep = &endpoints[endpoint*2+1];
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unsigned int size, csr;
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if(!ep->busy)
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return;
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select_endpoint(endpoint);
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while((csr = REG_USB_REG_OUTCSR) & (USB_OUTCSR_SENTSTALL|USB_OUTCSR_OUTPKTRDY))
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{
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logf("EPOUT_handler(%d): 0x%x", endpoint, csr);
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if(csr & USB_OUTCSR_SENTSTALL)
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{
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logf("stall sent, flushing fifo..");
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flushFIFO(ep);
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REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_SENTSTALL;
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return;
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}
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if(ep->use_dma)
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return;
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if(csr & USB_OUTCSR_OUTPKTRDY) /* There is a packet in the fifo */
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{
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size = REG_USB_REG_OUTCOUNT;
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readFIFO(ep, size);
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ep->received += size;
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/*if(csr & USB_OUTCSR_FFFULL)
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csr &= ~USB_OUTCSR_FFFULL;*/
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REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_OUTPKTRDY;
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logf("received: %d max length: %d", ep->received, ep->length);
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if(size < ep->fifo_size || ep->received >= ep->length)
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{
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usb_core_transfer_complete(endpoint, USB_DIR_OUT, 0, ep->received);
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if(ep->wait)
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wakeup_signal(&ep_wkup[endpoint*2+1]);
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logf("receive transfer_complete");
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ep->received = 0;
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ep->length = 0;
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ep->buf = NULL;
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ep->busy = false;
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return;
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}
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}
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}
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}
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static void EPDMA_handler(int number)
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{
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int endpoint=-1;
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unsigned int size=0;
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if(number == USB_INTR_DMA_BULKIN)
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endpoint = (REG_USB_REG_CNTL1 >> 4) & 0xF;
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else if(number == USB_INTR_DMA_BULKOUT)
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endpoint = (REG_USB_REG_CNTL2 >> 4) & 0xF;
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struct usb_endpoint* ep = &endpoints[endpoint];
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logf("DMA_BULK%d %d", number, endpoint);
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if(number == USB_INTR_DMA_BULKIN)
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size = (unsigned int)ep->buf - REG_USB_REG_ADDR1;
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else if(number == USB_INTR_DMA_BULKOUT)
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size = (unsigned int)ep->buf - REG_USB_REG_ADDR2;
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if(number == USB_INTR_DMA_BULKOUT)
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{
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/* Disable DMA */
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REG_USB_REG_CNTL2 = 0;
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__dcache_invalidate_all();
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select_endpoint(endpoint);
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/* Read out last packet manually */
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unsigned int lpack_size = REG_USB_REG_OUTCOUNT;
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if(lpack_size > 0)
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{
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ep->buf += ep->length - lpack_size;
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readFIFO(ep, lpack_size);
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REG_USB_REG_OUTCSR &= ~USB_OUTCSR_OUTPKTRDY;
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}
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}
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else if(number == USB_INTR_DMA_BULKIN && size % ep->fifo_size)
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/* If the last packet is less than MAXP, set INPKTRDY manually */
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REG_USB_REG_INCSR |= USB_INCSR_INPKTRDY;
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usb_core_transfer_complete(endpoint, EP_IS_IN(ep) ? USB_DIR_IN : USB_DIR_OUT,
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0, ep->length);
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ep->busy = false;
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ep->sent = 0;
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ep->length = 0;
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ep->buf = NULL;
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if(ep->wait)
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wakeup_signal(&ep_wkup[EP_NUMBER(ep)]);
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}
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static void setup_endpoint(struct usb_endpoint *ep)
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{
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int csr, csrh;
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select_endpoint(EP_NUMBER2(ep));
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ep->busy = false;
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ep->wait = false;
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ep->sent = 0;
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ep->length = 0;
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if(ep->type == ep_bulk)
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{
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if(REG_USB_REG_POWER & USB_POWER_HSMODE)
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ep->fifo_size = 512;
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else
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ep->fifo_size = 64;
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}
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if(EP_IS_IN(ep))
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{
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csr = (USB_INCSR_FF | USB_INCSR_CDT);
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csrh = USB_INCSRH_MODE;
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if(ep->use_dma)
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csrh |= (USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
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if(ep->type == ep_interrupt)
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csrh |= USB_INCSRH_FRCDATATOG;
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REG_USB_REG_INMAXP = ep->fifo_size;
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REG_USB_REG_INCSR = csr;
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REG_USB_REG_INCSRH = csrh;
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REG_USB_REG_INTRINE |= USB_INTR_EP(EP_NUMBER2(ep));
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}
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else
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{
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csr = (USB_OUTCSR_FF | USB_OUTCSR_CDT);
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csrh = 0;
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if(ep->type == ep_interrupt)
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csrh |= USB_OUTCSRH_DNYT;
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if(ep->use_dma)
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csrh |= (USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
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REG_USB_REG_OUTMAXP = ep->fifo_size;
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REG_USB_REG_OUTCSR = csr;
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REG_USB_REG_OUTCSRH = csrh;
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REG_USB_REG_INTROUTE |= USB_INTR_EP(EP_NUMBER2(ep));
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}
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}
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static void udc_reset(void)
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{
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/* From the datasheet:
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When a reset condition is detected on the USB, the controller performs the following actions:
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* Sets FAddr to 0.
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* Sets Index to 0.
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* Flushes all endpoint FIFOs.
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* Clears all control/status registers.
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* Enables all endpoint interrupts.
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* Generates a Reset interrupt.
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*/
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logf("udc_reset()");
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unsigned int i;
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/* EP0 init */
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ep0state = USB_EP0_IDLE;
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/* Disable interrupts */
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REG_USB_REG_INTRINE = 0;
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REG_USB_REG_INTROUTE = 0;
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REG_USB_REG_INTRUSBE = 0;
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/* Disable DMA */
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REG_USB_REG_CNTL1 = 0;
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REG_USB_REG_CNTL2 = 0;
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/* Reset address */
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REG_USB_REG_FADDR = 0;
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/* High speed, softconnect and suspend/resume */
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REG_USB_REG_POWER = (USB_POWER_SOFTCONN | USB_POWER_HSENAB | USB_POWER_SUSPENDM);
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/* Reset EP0 */
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select_endpoint(0);
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REG_USB_REG_CSR0 = (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_SVDSETUPEND);
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/* Reset other endpoints */
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for(i=2; i<TOTAL_EP(); i++)
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setup_endpoint(&endpoints[i]);
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/* Enable interrupts */
|
|
REG_USB_REG_INTRINE |= USB_INTR_EP0;
|
|
REG_USB_REG_INTRUSBE |= USB_INTR_RESET;
|
|
|
|
usb_core_bus_reset();
|
|
}
|
|
|
|
/* Interrupt handler */
|
|
void UDC(void)
|
|
{
|
|
/* Read interrupt registers */
|
|
unsigned char intrUSB = REG_USB_REG_INTRUSB & 0x07; /* Mask SOF */
|
|
unsigned short intrIn = REG_USB_REG_INTRIN;
|
|
unsigned short intrOut = REG_USB_REG_INTROUT;
|
|
unsigned char intrDMA = REG_USB_REG_INTR;
|
|
|
|
if(UNLIKELY(intrUSB == 0 && intrIn == 0 && intrOut == 0 && intrDMA == 0))
|
|
return;
|
|
|
|
logf("%x %x %x %x", intrUSB, intrIn, intrOut, intrDMA);
|
|
|
|
/* EPIN & EPOUT are all handled in DMA */
|
|
if(intrIn & USB_INTR_EP0)
|
|
EP0_handler();
|
|
if(intrIn & USB_INTR_INEP1)
|
|
EPIN_handler(1);
|
|
if(intrIn & USB_INTR_INEP2)
|
|
EPIN_handler(2);
|
|
if(intrOut & USB_INTR_OUTEP1)
|
|
EPOUT_handler(1);
|
|
if(intrOut & USB_INTR_OUTEP2)
|
|
EPOUT_handler(2);
|
|
if(intrUSB & USB_INTR_RESET)
|
|
udc_reset();
|
|
if(intrUSB & USB_INTR_SUSPEND)
|
|
{
|
|
logf("USB suspend");
|
|
}
|
|
if(intrUSB & USB_INTR_RESUME)
|
|
{
|
|
logf("USB resume");
|
|
}
|
|
if(intrDMA & USB_INTR_DMA_BULKIN)
|
|
EPDMA_handler(USB_INTR_DMA_BULKIN);
|
|
if(intrDMA & USB_INTR_DMA_BULKOUT)
|
|
EPDMA_handler(USB_INTR_DMA_BULKOUT);
|
|
}
|
|
|
|
bool usb_drv_stalled(int endpoint, bool in)
|
|
{
|
|
endpoint &= 0x7F;
|
|
|
|
logf("usb_drv_stalled(%d, %s)", endpoint, in?"IN":"OUT");
|
|
|
|
select_endpoint(endpoint);
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
return (REG_USB_REG_CSR0 & USB_CSR0_SENDSTALL) != 0;
|
|
else
|
|
{
|
|
if(in)
|
|
return (REG_USB_REG_INCSR & USB_INCSR_SENDSTALL) != 0;
|
|
else
|
|
return (REG_USB_REG_OUTCSR & USB_OUTCSR_SENDSTALL) != 0;
|
|
}
|
|
}
|
|
|
|
void usb_drv_stall(int endpoint, bool stall, bool in)
|
|
{
|
|
endpoint &= 0x7F;
|
|
|
|
logf("usb_drv_stall(%d,%s,%s)", endpoint, stall?"Y":"N", in?"IN":"OUT");
|
|
|
|
select_endpoint(endpoint);
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL;
|
|
else
|
|
REG_USB_REG_CSR0 &= ~USB_CSR0_SENDSTALL;
|
|
}
|
|
else
|
|
{
|
|
if(in)
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_INCSR |= USB_INCSR_SENDSTALL;
|
|
else
|
|
REG_USB_REG_INCSR = (REG_USB_REG_INCSR & ~USB_INCSR_SENDSTALL) | USB_INCSR_CDT;
|
|
}
|
|
else
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_OUTCSR |= USB_OUTCSR_SENDSTALL;
|
|
else
|
|
REG_USB_REG_OUTCSR = (REG_USB_REG_OUTCSR & ~USB_OUTCSR_SENDSTALL) | USB_OUTCSR_CDT;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool usb_drv_connected(void)
|
|
{
|
|
return USB_DRV_CONNECTED();
|
|
}
|
|
|
|
int usb_detect(void)
|
|
{
|
|
return usb_drv_connected() ? USB_INSERTED : USB_EXTRACTED;
|
|
}
|
|
|
|
void usb_init_device(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
USB_INIT_GPIO();
|
|
#ifdef USB_GPIO_IRQ
|
|
system_enable_irq(IRQ_GPIO_UDC_DETE);
|
|
#endif
|
|
system_enable_irq(IRQ_UDC);
|
|
|
|
for(i=0; i<TOTAL_EP(); i++)
|
|
wakeup_init(&ep_wkup[i]);
|
|
}
|
|
|
|
#ifdef USB_GPIO_IRQ
|
|
static unsigned long last_tick;
|
|
void USB_GPIO_IRQ(void)
|
|
{
|
|
/* Prevent enabled-disabled bouncing */
|
|
if(current_tick - last_tick > HZ/16)
|
|
{
|
|
usb_status_event(usb_detect());
|
|
last_tick = current_tick;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void usb_enable(bool on)
|
|
{
|
|
if(on)
|
|
usb_core_init();
|
|
else
|
|
usb_core_exit();
|
|
}
|
|
|
|
void usb_attach(void)
|
|
{
|
|
usb_enable(true);
|
|
}
|
|
|
|
void usb_drv_init(void)
|
|
{
|
|
logf("usb_drv_init()");
|
|
|
|
/* Set this bit to allow the UDC entering low-power mode when
|
|
* there are no actions on the USB bus.
|
|
* UDC still works during this bit was set.
|
|
*/
|
|
//__cpm_stop_udc();
|
|
__cpm_start_udc();
|
|
|
|
/* Enable the USB PHY */
|
|
REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
|
|
|
|
/* Dis- and reconnect from USB */
|
|
REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
|
|
REG_USB_REG_POWER |= USB_POWER_SOFTCONN;
|
|
|
|
udc_reset();
|
|
}
|
|
|
|
void usb_drv_exit(void)
|
|
{
|
|
logf("usb_drv_exit()");
|
|
|
|
/* Disable interrupts */
|
|
REG_USB_REG_INTRINE = 0;
|
|
REG_USB_REG_INTROUTE = 0;
|
|
REG_USB_REG_INTRUSBE = 0;
|
|
|
|
/* Disable DMA */
|
|
REG_USB_REG_CNTL1 = 0;
|
|
REG_USB_REG_CNTL2 = 0;
|
|
|
|
/* Disconnect from USB */
|
|
REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
|
|
|
|
/* Disable the USB PHY */
|
|
REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
|
|
|
|
__cpm_stop_udc();
|
|
}
|
|
|
|
void usb_drv_set_address(int address)
|
|
{
|
|
logf("set adr: %d", address);
|
|
|
|
REG_USB_REG_FADDR = address;
|
|
}
|
|
|
|
int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
|
|
{
|
|
int flags;
|
|
endpoint &= 0x7F;
|
|
|
|
logf("usb_drv_send(%d, 0x%x, %d)", endpoint, (int)ptr, length);
|
|
|
|
if(endpoint == EP_CONTROL && ptr == NULL && length == 0)
|
|
return 0; /* ACK request, handled by the USB controller */
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
{
|
|
flags = disable_irq_save();
|
|
endpoints[0].buf = ptr;
|
|
endpoints[0].sent = 0;
|
|
endpoints[0].length = length;
|
|
ep0state = USB_EP0_TX;
|
|
EP0_send();
|
|
restore_irq(flags);
|
|
|
|
return 0;
|
|
}
|
|
else
|
|
{
|
|
flags = disable_irq_save();
|
|
endpoints[endpoint*2].buf = ptr;
|
|
endpoints[endpoint*2].sent = 0;
|
|
endpoints[endpoint*2].length = length;
|
|
endpoints[endpoint*2].busy = true;
|
|
if(endpoints[endpoint*2].use_dma)
|
|
{
|
|
//dma_cache_wback_inv((unsigned long)ptr, length);
|
|
__dcache_writeback_all();
|
|
REG_USB_REG_ADDR1 = PHYSADDR((unsigned long)ptr);
|
|
REG_USB_REG_COUNT1 = length;
|
|
REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
|
|
USB_CNTL_DIR_IN | USB_CNTL_ENA |
|
|
USB_CNTL_EP(endpoint) | USB_CNTL_BURST_16);
|
|
}
|
|
else
|
|
EPIN_handler(endpoint);
|
|
|
|
restore_irq(flags);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int usb_drv_send(int endpoint, void* ptr, int length)
|
|
{
|
|
int ret;
|
|
endpoint &= 0x7F;
|
|
|
|
if(endpoint == EP_CONTROL && ptr == NULL && length == 0)
|
|
return 0; /* ACK request, handled by the USB controller */
|
|
|
|
endpoints[endpoint*2].wait = true;
|
|
ret = usb_drv_send_nonblocking(endpoint, ptr, length);
|
|
wakeup_wait(&ep_wkup[endpoint*2], TIMEOUT_BLOCK);
|
|
endpoints[endpoint*2].wait = false;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int usb_drv_recv(int endpoint, void* ptr, int length)
|
|
{
|
|
int flags;
|
|
endpoint &= 0x7F;
|
|
|
|
logf("usb_drv_recv(%d, 0x%x, %d)", endpoint, (int)ptr, length);
|
|
|
|
if(endpoint == EP_CONTROL && ptr == NULL && length == 0)
|
|
return 0; /* ACK request, handled by the USB controller */
|
|
else
|
|
{
|
|
flags = disable_irq_save();
|
|
endpoints[endpoint*2+1].buf = ptr;
|
|
endpoints[endpoint*2+1].received = 0;
|
|
endpoints[endpoint*2+1].length = length;
|
|
endpoints[endpoint*2+1].busy = true;
|
|
if(endpoints[endpoint*2+1].use_dma)
|
|
{
|
|
//dma_cache_wback_inv((unsigned long)ptr, length);
|
|
__dcache_writeback_all();
|
|
REG_USB_REG_ADDR2 = PHYSADDR((unsigned long)ptr);
|
|
REG_USB_REG_COUNT2 = length;
|
|
REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
|
|
USB_CNTL_ENA | USB_CNTL_EP(endpoint) |
|
|
USB_CNTL_BURST_16);
|
|
}
|
|
else
|
|
EPOUT_handler(endpoint);
|
|
|
|
restore_irq(flags);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void usb_drv_set_test_mode(int mode)
|
|
{
|
|
logf("usb_drv_set_test_mode(%d)", mode);
|
|
|
|
switch(mode)
|
|
{
|
|
case 0:
|
|
REG_USB_REG_TESTMODE &= ~USB_TEST_ALL;
|
|
break;
|
|
case 1:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_J;
|
|
break;
|
|
case 2:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_K;
|
|
break;
|
|
case 3:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_SE0NAK;
|
|
break;
|
|
case 4:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_PACKET;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int usb_drv_port_speed(void)
|
|
{
|
|
return (REG_USB_REG_POWER & USB_POWER_HSMODE) ? 1 : 0;
|
|
}
|
|
|
|
void usb_drv_cancel_all_transfers(void)
|
|
{
|
|
logf("usb_drv_cancel_all_transfers()");
|
|
|
|
unsigned int i, flags;
|
|
flags = disable_irq_save();
|
|
|
|
for(i=0; i<TOTAL_EP(); i++)
|
|
{
|
|
if(i >= 2)
|
|
endpoints[i].buf = NULL;
|
|
|
|
endpoints[i].sent = 0;
|
|
endpoints[i].length = 0;
|
|
|
|
select_endpoint(i/2);
|
|
flushFIFO(&endpoints[i]);
|
|
}
|
|
restore_irq(flags);
|
|
|
|
ep0state = USB_EP0_IDLE;
|
|
}
|
|
|
|
void usb_drv_release_endpoint(int ep)
|
|
{
|
|
(void)ep;
|
|
logf("usb_drv_release_endpoint(%d, %s)", (ep & 0x7F), (ep >> 7) ? "IN" : "OUT");
|
|
}
|
|
|
|
int usb_drv_request_endpoint(int type, int dir)
|
|
{
|
|
logf("usb_drv_request_endpoint(%d, %s)", type, (dir == USB_DIR_IN) ? "IN" : "OUT");
|
|
|
|
dir &= USB_ENDPOINT_DIR_MASK;
|
|
type &= USB_ENDPOINT_XFERTYPE_MASK;
|
|
|
|
/* There are only 3+2 endpoints, so hardcode this ... */
|
|
switch(type)
|
|
{
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
if(dir == USB_DIR_IN)
|
|
return (1 | USB_DIR_IN);
|
|
else
|
|
return (1 | USB_DIR_OUT);
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
|
if(dir == USB_DIR_IN)
|
|
return (2 | USB_DIR_IN);
|
|
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|