274 lines
16 KiB
C
274 lines
16 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3700:3.2.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3700__DRI__H__
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#define __HEADERGEN__STMP3700__DRI__H__
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#define REGS_DRI_BASE (0x80074000)
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#define REGS_DRI_VERSION "3.2.0"
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/**
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* Register: HW_DRI_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_DRI_CTRL (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x0))
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#define HW_DRI_CTRL_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x4))
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#define HW_DRI_CTRL_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0x8))
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#define HW_DRI_CTRL_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x0 + 0xc))
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#define BP_DRI_CTRL_SFTRST 31
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#define BM_DRI_CTRL_SFTRST 0x80000000
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#define BV_DRI_CTRL_SFTRST__RUN 0x0
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#define BV_DRI_CTRL_SFTRST__RESET 0x1
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#define BF_DRI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BF_DRI_CTRL_SFTRST_V(v) ((BV_DRI_CTRL_SFTRST__##v << 31) & 0x80000000)
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#define BP_DRI_CTRL_CLKGATE 30
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#define BM_DRI_CTRL_CLKGATE 0x40000000
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#define BV_DRI_CTRL_CLKGATE__RUN 0x0
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#define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1
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#define BF_DRI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BF_DRI_CTRL_CLKGATE_V(v) ((BV_DRI_CTRL_CLKGATE__##v << 30) & 0x40000000)
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#define BP_DRI_CTRL_ENABLE_INPUTS 29
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#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
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#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0
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#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1
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#define BF_DRI_CTRL_ENABLE_INPUTS(v) (((v) << 29) & 0x20000000)
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#define BF_DRI_CTRL_ENABLE_INPUTS_V(v) ((BV_DRI_CTRL_ENABLE_INPUTS__##v << 29) & 0x20000000)
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#define BP_DRI_CTRL_STOP_ON_OFLOW_ERROR 26
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#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x4000000
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#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0
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#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1
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#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR(v) (((v) << 26) & 0x4000000)
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#define BF_DRI_CTRL_STOP_ON_OFLOW_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__##v << 26) & 0x4000000)
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#define BP_DRI_CTRL_STOP_ON_PILOT_ERROR 25
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#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x2000000
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#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0
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#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1
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#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR(v) (((v) << 25) & 0x2000000)
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#define BF_DRI_CTRL_STOP_ON_PILOT_ERROR_V(v) ((BV_DRI_CTRL_STOP_ON_PILOT_ERROR__##v << 25) & 0x2000000)
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#define BP_DRI_CTRL_DMA_DELAY_COUNT 16
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#define BM_DRI_CTRL_DMA_DELAY_COUNT 0x1f0000
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#define BF_DRI_CTRL_DMA_DELAY_COUNT(v) (((v) << 16) & 0x1f0000)
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#define BP_DRI_CTRL_REACQUIRE_PHASE 15
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#define BM_DRI_CTRL_REACQUIRE_PHASE 0x8000
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#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0
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#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1
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#define BF_DRI_CTRL_REACQUIRE_PHASE(v) (((v) << 15) & 0x8000)
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#define BF_DRI_CTRL_REACQUIRE_PHASE_V(v) ((BV_DRI_CTRL_REACQUIRE_PHASE__##v << 15) & 0x8000)
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#define BP_DRI_CTRL_OVERFLOW_IRQ_EN 11
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#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x800
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#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0
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#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1
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#define BF_DRI_CTRL_OVERFLOW_IRQ_EN(v) (((v) << 11) & 0x800)
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#define BF_DRI_CTRL_OVERFLOW_IRQ_EN_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ_EN__##v << 11) & 0x800)
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#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 10
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#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x400
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#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0
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#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1
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#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN(v) (((v) << 10) & 0x400)
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#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__##v << 10) & 0x400)
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#define BP_DRI_CTRL_ATTENTION_IRQ_EN 9
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#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x200
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#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0
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#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1
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#define BF_DRI_CTRL_ATTENTION_IRQ_EN(v) (((v) << 9) & 0x200)
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#define BF_DRI_CTRL_ATTENTION_IRQ_EN_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ_EN__##v << 9) & 0x200)
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#define BP_DRI_CTRL_OVERFLOW_IRQ 3
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#define BM_DRI_CTRL_OVERFLOW_IRQ 0x8
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#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0
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#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1
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#define BF_DRI_CTRL_OVERFLOW_IRQ(v) (((v) << 3) & 0x8)
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#define BF_DRI_CTRL_OVERFLOW_IRQ_V(v) ((BV_DRI_CTRL_OVERFLOW_IRQ__##v << 3) & 0x8)
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#define BP_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 2
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#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x4
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#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0
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#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1
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#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ(v) (((v) << 2) & 0x4)
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#define BF_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_V(v) ((BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__##v << 2) & 0x4)
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#define BP_DRI_CTRL_ATTENTION_IRQ 1
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#define BM_DRI_CTRL_ATTENTION_IRQ 0x2
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#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0
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#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1
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#define BF_DRI_CTRL_ATTENTION_IRQ(v) (((v) << 1) & 0x2)
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#define BF_DRI_CTRL_ATTENTION_IRQ_V(v) ((BV_DRI_CTRL_ATTENTION_IRQ__##v << 1) & 0x2)
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#define BP_DRI_CTRL_RUN 0
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#define BM_DRI_CTRL_RUN 0x1
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#define BV_DRI_CTRL_RUN__HALT 0x0
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#define BV_DRI_CTRL_RUN__RUN 0x1
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#define BF_DRI_CTRL_RUN(v) (((v) << 0) & 0x1)
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#define BF_DRI_CTRL_RUN_V(v) ((BV_DRI_CTRL_RUN__##v << 0) & 0x1)
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/**
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* Register: HW_DRI_TIMING
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* Address: 0x10
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* SCT: no
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*/
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#define HW_DRI_TIMING (*(volatile unsigned long *)(REGS_DRI_BASE + 0x10))
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#define BP_DRI_TIMING_PILOT_REP_RATE 16
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#define BM_DRI_TIMING_PILOT_REP_RATE 0xf0000
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#define BF_DRI_TIMING_PILOT_REP_RATE(v) (((v) << 16) & 0xf0000)
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#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
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#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0xff
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#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) (((v) << 0) & 0xff)
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/**
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* Register: HW_DRI_STAT
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* Address: 0x20
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* SCT: no
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*/
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#define HW_DRI_STAT (*(volatile unsigned long *)(REGS_DRI_BASE + 0x20))
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#define BP_DRI_STAT_DRI_PRESENT 31
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#define BM_DRI_STAT_DRI_PRESENT 0x80000000
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#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0
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#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1
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#define BF_DRI_STAT_DRI_PRESENT(v) (((v) << 31) & 0x80000000)
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#define BF_DRI_STAT_DRI_PRESENT_V(v) ((BV_DRI_STAT_DRI_PRESENT__##v << 31) & 0x80000000)
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#define BP_DRI_STAT_PILOT_PHASE 16
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#define BM_DRI_STAT_PILOT_PHASE 0xf0000
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#define BF_DRI_STAT_PILOT_PHASE(v) (((v) << 16) & 0xf0000)
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#define BP_DRI_STAT_OVERFLOW_IRQ_SUMMARY 3
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#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x8
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#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0
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#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1
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#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY(v) (((v) << 3) & 0x8)
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#define BF_DRI_STAT_OVERFLOW_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__##v << 3) & 0x8)
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#define BP_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 2
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#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x4
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#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
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#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1
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#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY(v) (((v) << 2) & 0x4)
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#define BF_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__##v << 2) & 0x4)
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#define BP_DRI_STAT_ATTENTION_IRQ_SUMMARY 1
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#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x2
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#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0
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#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1
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#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY(v) (((v) << 1) & 0x2)
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#define BF_DRI_STAT_ATTENTION_IRQ_SUMMARY_V(v) ((BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__##v << 1) & 0x2)
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/**
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* Register: HW_DRI_DATA
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* Address: 0x30
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* SCT: no
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*/
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#define HW_DRI_DATA (*(volatile unsigned long *)(REGS_DRI_BASE + 0x30))
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#define BP_DRI_DATA_DATA 0
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#define BM_DRI_DATA_DATA 0xffffffff
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#define BF_DRI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_DRI_DEBUG0
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* Address: 0x40
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* SCT: yes
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*/
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#define HW_DRI_DEBUG0 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x0))
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#define HW_DRI_DEBUG0_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x4))
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#define HW_DRI_DEBUG0_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0x8))
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#define HW_DRI_DEBUG0_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x40 + 0xc))
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#define BP_DRI_DEBUG0_DMAREQ 31
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#define BM_DRI_DEBUG0_DMAREQ 0x80000000
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#define BF_DRI_DEBUG0_DMAREQ(v) (((v) << 31) & 0x80000000)
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#define BP_DRI_DEBUG0_DMACMDKICK 30
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#define BM_DRI_DEBUG0_DMACMDKICK 0x40000000
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#define BF_DRI_DEBUG0_DMACMDKICK(v) (((v) << 30) & 0x40000000)
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#define BP_DRI_DEBUG0_DRI_CLK_INPUT 29
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#define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000
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#define BF_DRI_DEBUG0_DRI_CLK_INPUT(v) (((v) << 29) & 0x20000000)
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#define BP_DRI_DEBUG0_DRI_DATA_INPUT 28
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#define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000
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#define BF_DRI_DEBUG0_DRI_DATA_INPUT(v) (((v) << 28) & 0x10000000)
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#define BP_DRI_DEBUG0_TEST_MODE 27
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#define BM_DRI_DEBUG0_TEST_MODE 0x8000000
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#define BF_DRI_DEBUG0_TEST_MODE(v) (((v) << 27) & 0x8000000)
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#define BP_DRI_DEBUG0_PILOT_REP_RATE 26
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#define BM_DRI_DEBUG0_PILOT_REP_RATE 0x4000000
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#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0
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#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1
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#define BF_DRI_DEBUG0_PILOT_REP_RATE(v) (((v) << 26) & 0x4000000)
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#define BF_DRI_DEBUG0_PILOT_REP_RATE_V(v) ((BV_DRI_DEBUG0_PILOT_REP_RATE__##v << 26) & 0x4000000)
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#define BP_DRI_DEBUG0_SPARE 18
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#define BM_DRI_DEBUG0_SPARE 0x3fc0000
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#define BF_DRI_DEBUG0_SPARE(v) (((v) << 18) & 0x3fc0000)
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#define BP_DRI_DEBUG0_FRAME 0
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#define BM_DRI_DEBUG0_FRAME 0x3ffff
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#define BF_DRI_DEBUG0_FRAME(v) (((v) << 0) & 0x3ffff)
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/**
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* Register: HW_DRI_DEBUG1
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* Address: 0x50
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* SCT: yes
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*/
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#define HW_DRI_DEBUG1 (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x0))
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#define HW_DRI_DEBUG1_SET (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x4))
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#define HW_DRI_DEBUG1_CLR (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0x8))
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#define HW_DRI_DEBUG1_TOG (*(volatile unsigned long *)(REGS_DRI_BASE + 0x50 + 0xc))
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#define BP_DRI_DEBUG1_INVERT_PILOT 31
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#define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000
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#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0
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#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1
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#define BF_DRI_DEBUG1_INVERT_PILOT(v) (((v) << 31) & 0x80000000)
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#define BF_DRI_DEBUG1_INVERT_PILOT_V(v) ((BV_DRI_DEBUG1_INVERT_PILOT__##v << 31) & 0x80000000)
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#define BP_DRI_DEBUG1_INVERT_ATTENTION 30
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#define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000
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#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0
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#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1
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#define BF_DRI_DEBUG1_INVERT_ATTENTION(v) (((v) << 30) & 0x40000000)
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#define BF_DRI_DEBUG1_INVERT_ATTENTION_V(v) ((BV_DRI_DEBUG1_INVERT_ATTENTION__##v << 30) & 0x40000000)
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#define BP_DRI_DEBUG1_INVERT_DRI_DATA 29
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#define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000
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#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0
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#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1
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#define BF_DRI_DEBUG1_INVERT_DRI_DATA(v) (((v) << 29) & 0x20000000)
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#define BF_DRI_DEBUG1_INVERT_DRI_DATA_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_DATA__##v << 29) & 0x20000000)
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#define BP_DRI_DEBUG1_INVERT_DRI_CLOCK 28
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#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000
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#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0
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#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1
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#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK(v) (((v) << 28) & 0x10000000)
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#define BF_DRI_DEBUG1_INVERT_DRI_CLOCK_V(v) ((BV_DRI_DEBUG1_INVERT_DRI_CLOCK__##v << 28) & 0x10000000)
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#define BP_DRI_DEBUG1_REVERSE_FRAME 27
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#define BM_DRI_DEBUG1_REVERSE_FRAME 0x8000000
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#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0
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#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1
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#define BF_DRI_DEBUG1_REVERSE_FRAME(v) (((v) << 27) & 0x8000000)
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#define BF_DRI_DEBUG1_REVERSE_FRAME_V(v) ((BV_DRI_DEBUG1_REVERSE_FRAME__##v << 27) & 0x8000000)
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#define BP_DRI_DEBUG1_SWIZZLED_FRAME 0
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#define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x3ffff
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#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) (((v) << 0) & 0x3ffff)
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/**
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* Register: HW_DRI_VERSION
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* Address: 0x60
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* SCT: no
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*/
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#define HW_DRI_VERSION (*(volatile unsigned long *)(REGS_DRI_BASE + 0x60))
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#define BP_DRI_VERSION_MAJOR 24
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#define BM_DRI_VERSION_MAJOR 0xff000000
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#define BF_DRI_VERSION_MAJOR(v) (((v) << 24) & 0xff000000)
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#define BP_DRI_VERSION_MINOR 16
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#define BM_DRI_VERSION_MINOR 0xff0000
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#define BF_DRI_VERSION_MINOR(v) (((v) << 16) & 0xff0000)
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#define BP_DRI_VERSION_STEP 0
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#define BM_DRI_VERSION_STEP 0xffff
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#define BF_DRI_VERSION_STEP(v) (((v) << 0) & 0xffff)
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#endif /* __HEADERGEN__STMP3700__DRI__H__ */
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