125 lines
4.3 KiB
C
125 lines
4.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "mmu-arm.h"
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#include "panic.h"
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#include "clock-target.h" /* CPUFREQ_* are defined here */
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#include "clkctrl-imx233.h"
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#include "power-imx233.h"
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/* Digital control */
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#define HW_DIGCTL_BASE 0x8001C000
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#define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
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#define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
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#define HW_DIGCTL_HCLKCOUNT (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20))
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#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
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/* USB Phy */
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#define HW_USBPHY_BASE 0x8007C000
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#define HW_USBPHY_PWD (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
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#define HW_USBPHY_PWD__ALL (7 << 10 | 0xf << 17)
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#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
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/* Interrupt collector */
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#define HW_ICOLL_BASE 0x80000000
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#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
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#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
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#define HW_ICOLL_LEVELACK__LEVEL0 0x1
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#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
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#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
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#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
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#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
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#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
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#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
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#define HW_ICOLL_INTERRUPT__ENABLE 0x4
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#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
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#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
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#define INT_SRC_SSP2_ERROR 2
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#define INT_SRC_VDD5V 3
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#define INT_SRC_DAC_DMA 5
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#define INT_SRC_DAC_ERROR 6
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#define INT_SRC_USB_CTRL 11
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#define INT_SRC_SSP1_DMA 14
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#define INT_SRC_SSP1_ERROR 15
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#define INT_SRC_GPIO0 16
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#define INT_SRC_GPIO1 17
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#define INT_SRC_GPIO2 18
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#define INT_SRC_GPIO(i) (INT_SRC_GPIO0 + (i))
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#define INT_SRC_SSP2_DMA 20
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#define INT_SRC_I2C_DMA 26
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#define INT_SRC_I2C_ERROR 27
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#define INT_SRC_TIMER(nr) (28 + (nr))
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#define INT_SRC_LRADC_CHx(x) (37 + (x))
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#define INT_SRC_LCDIF_DMA 45
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#define INT_SRC_LCDIF_ERROR 46
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#define INT_SRC_DCP 54
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#define INT_SRC_NR_SOURCES 66
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/**
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* Absolute maximum CPU speed: 454.74 MHz
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* Intermediate CPU speeds: 392.73 MHz, 360MHz, 261.82 MHz, 64 MHz
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* Absolute minimum CPU speed: 24 MHz */
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#define IMX233_CPUFREQ_454_MHz 454740000
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#define IMX233_CPUFREQ_392_MHz 392730000
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#define IMX233_CPUFREQ_360_MHz 360000000
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#define IMX233_CPUFREQ_261_MHz 261820000
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#define IMX233_CPUFREQ_64_MHz 64000000
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#define IMX233_CPUFREQ_24_MHz 24000000
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#define CPUFREQ_DEFAULT IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_NORMAL IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz
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#define CPUFREQ_SLEEP IMX233_CPUFREQ_454_MHz
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void imx233_enable_interrupt(int src, bool enable);
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void imx233_softirq(int src, bool enable);
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void udelay(unsigned us);
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay);
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void imx233_reset_block(volatile uint32_t *block_reg);
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void power_off(void);
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void imx233_enable_usb_controller(bool enable);
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void imx233_enable_usb_phy(bool enable);
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void udelay(unsigned usecs);
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static inline void mdelay(unsigned msecs)
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{
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udelay(1000 * msecs);
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}
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void usb_insert_int(void);
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void usb_remove_int(void);
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bool dbg_hw_target_info(void);
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#endif /* SYSTEM_TARGET_H */
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