9f27dc2103
- polling/IRQ modes for Tx/Rx (TODO?: DMA) - fine adjust for Tx/Rx bitrates - auto bauding using HW circuitry - status and stats in debug screen Change-Id: I8650957063bc6d274d92eba2779d93ae73453fb6
321 lines
12 KiB
C
321 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __UC8702_H__
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#define __UC8702_H__
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#include <stdint.h>
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#include <stdbool.h>
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/* s5l8702 UART controller (UC8702):
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*
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* This UART is similar to the UART included in s5l8700 (see also
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* s3c2416 and s3c6400 datasheets), UC8702 adds fine tunning for
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* Tx/Rx bitrate and autobauding.
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*/
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/*#define UC8702_DEBUG*/
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/*
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* uc8702 HW definitions
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*/
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#define UART_PORT_MAX 4
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#define UART_FIFO_SIZE 16
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#define UART_PORT_BASE(b,i) ((b) + 0x4000 * (i))
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/*
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* controller registers
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*/
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#define REG32_PTR_T volatile uint32_t *
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#define ULCON(ba) (*((REG32_PTR_T)((ba) + 0x00))) /* line control */
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#define UCON(ba) (*((REG32_PTR_T)((ba) + 0x04))) /* control */
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#define UFCON(ba) (*((REG32_PTR_T)((ba) + 0x08))) /* FIFO control */
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#define UMCON(ba) (*((REG32_PTR_T)((ba) + 0x0C))) /* modem control */
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#define UTRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x10))) /* Tx/Rx status */
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#define UERSTAT(ba) (*((REG32_PTR_T)((ba) + 0x14))) /* Rx error status */
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#define UFSTAT(ba) (*((REG32_PTR_T)((ba) + 0x18))) /* FIFO status */
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#define UMSTAT(ba) (*((REG32_PTR_T)((ba) + 0x1C))) /* modem status */
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#define UTXH(ba) (*((REG32_PTR_T)((ba) + 0x20))) /* transmission hold */
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#define URXH(ba) (*((REG32_PTR_T)((ba) + 0x24))) /* receive buffer */
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#define UBRDIV(ba) (*((REG32_PTR_T)((ba) + 0x28))) /* baud rate divisor */
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#define UABRCNT(ba) (*((REG32_PTR_T)((ba) + 0x2c))) /* autobaud counter */
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#define UABRSTAT(ba) (*((REG32_PTR_T)((ba) + 0x30))) /* autobaud status */
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#define UBRCONTX(ba) (*((REG32_PTR_T)((ba) + 0x34))) /* Tx frame config */
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#define UBRCONRX(ba) (*((REG32_PTR_T)((ba) + 0x38))) /* Rx frame config */
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/* ULCON register */
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#define ULCON_DATA_BITS_MASK 0x3
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#define ULCON_DATA_BITS_POS 0
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#define ULCON_DATA_BITS_5 0
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#define ULCON_DATA_BITS_6 1
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#define ULCON_DATA_BITS_7 2
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#define ULCON_DATA_BITS_8 3
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#define ULCON_STOP_BITS_MASK 0x1
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#define ULCON_STOP_BITS_POS 2
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#define ULCON_STOP_BITS_1 0
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#define ULCON_STOP_BITS_2 1
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#define ULCON_PARITY_MASK 0x7
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#define ULCON_PARITY_POS 3
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#define ULCON_PARITY_NONE 0
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#define ULCON_PARITY_ODD 4
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#define ULCON_PARITY_EVEN 5
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#define ULCON_PARITY_FORCE_1 6
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#define ULCON_PARITY_FORCE_0 7
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#define ULCON_INFRARED_EN_BIT (1 << 6)
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/* UCON register */
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#define UCON_RX_MODE_MASK 0x3
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#define UCON_RX_MODE_POS 0
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#define UCON_TX_MODE_MASK 0x3
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#define UCON_TX_MODE_POS 2
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#define UCON_MODE_DISABLED 0
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#define UCON_MODE_INTREQ 1 /* INT request or polling mode */
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#define UCON_MODE_UNDEFINED 2 /* Not defined, DMAREQ signal 1 ??? */
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#define UCON_MODE_DMAREQ 3 /* DMA request (signal 0) */
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#define UCON_SEND_BREAK_BIT (1 << 4)
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#define UCON_LOOPBACK_BIT (1 << 5)
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#define UCON_RX_TOUT_EN_BIT (1 << 7) /* Rx timeout enable */
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#define UCON_CLKSEL_MASK 0x1
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#define UCON_CLKSEL_POS 10
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#define UCON_CLKSEL_PCLK 0 /* internal */
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#define UCON_CLKSEL_ECLK 1 /* external */
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#define UCON_RX_TOUT_INT_BIT (1 << 11) /* Rx timeout INT enable */
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#define UCON_RX_INT_BIT (1 << 12) /* Rx INT enable */
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#define UCON_TX_INT_BIT (1 << 13) /* Tx INT enable */
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#define UCON_ERR_INT_BIT (1 << 14) /* Rx error INT enable */
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#define UCON_MODEM_INT_BIT (1 << 15) /* modem INT enable (TBC) */
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#define UCON_AUTOBR_INT_BIT (1 << 16) /* autobauding INT enable */
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#define UCON_AUTOBR_START_BIT (1 << 17) /* autobauding start/stop */
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/* UFCON register */
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#define UFCON_FIFO_ENABLE_BIT (1 << 0)
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#define UFCON_RX_FIFO_RST_BIT (1 << 1)
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#define UFCON_TX_FIFO_RST_BIT (1 << 2)
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#define UFCON_RX_FIFO_TRG_MASK 0x3
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#define UFCON_RX_FIFO_TRG_POS 4
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#define UFCON_RX_FIFO_TRG_4 0
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#define UFCON_RX_FIFO_TRG_8 1
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#define UFCON_RX_FIFO_TRG_12 2
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#define UFCON_RX_FIFO_TRG_16 3
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#define UFCON_TX_FIFO_TRG_MASK 0x3
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#define UFCON_TX_FIFO_TRG_POS 6
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#define UFCON_TX_FIFO_TRG_EMPTY 0
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#define UFCON_TX_FIFO_TRG_4 1
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#define UFCON_TX_FIFO_TRG_8 2
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#define UFCON_TX_FIFO_TRG_12 3
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/* UMCON register */
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#define UMCON_RTS_BIT (1 << 0)
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#define UMCON_AUTO_FLOW_CTRL_BIT (1 << 4)
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/* UTRSTAT register */
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#define UTRSTAT_RXBUF_RDY_BIT (1 << 0)
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#define UTRSTAT_TXBUF_EMPTY_BIT (1 << 1)
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#define UTRSTAT_TX_EMPTY_BIT (1 << 2)
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#define UTRSTAT_RX_TOUT_INT_BIT (1 << 3) /* Rx timeout INT status */
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#define UTRSTAT_RX_INT_BIT (1 << 4)
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#define UTRSTAT_TX_INT_BIT (1 << 5)
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#define UTRSTAT_ERR_INT_BIT (1 << 6)
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#define UTRSTAT_MODEM_INT_BIT (1 << 7) /* modem INT status (TBC) */
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#define UTRSTAT_AUTOBR_INT_BIT (1 << 8) /* autobauding INT status */
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/* UERSTAT register */
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#define UERSTAT_OVERRUN_BIT (1 << 0)
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#define UERSTAT_PARITY_ERR_BIT (1 << 1)
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#define UERSTAT_FRAME_ERR_BIT (1 << 2)
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#define UERSTAT_BREAK_DETECT_BIT (1 << 3)
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/* UFSTAT register */
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#define UFSTAT_RX_FIFO_CNT_MASK 0xf
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#define UFSTAT_RX_FIFO_CNT_POS 0
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#define UFSTAT_TX_FIFO_CNT_MASK 0xf
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#define UFSTAT_TX_FIFO_CNT_POS 4
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#define UFSTAT_RX_FIFO_FULL_BIT (1 << 8)
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#define UFSTAT_TX_FIFO_FULL_BIT (1 << 9)
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#define UFSTAT_RX_FIFO_ERR_BIT (1 << 10) /* clears when reading UERSTAT
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for the last pending error */
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/* UMSTAT register */
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#define UMSTAT_CTS_ACTIVE_BIT (1 << 0)
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#define UMSTAT_CTS_DELTA_BIT (1 << 4)
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/* Bitrate:
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*
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* Master UCLK clock is divided by 16 to serialize data, UBRDIV is
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* used to configure nominal bit width, NBW = (UBRDIV+1)*16 in UCLK
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* clock ticks.
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*
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* Fine tuning works shrining/expanding each individual bit of each
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* frame. Each bit width can be incremented/decremented by 1/16 of
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* nominal bit width, it seems UCLK is divided by 17 for expanded
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* bits and divided by 15 for compressed bits. A whole frame of N
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* bits can be shrined or expanded up to (NBW * N / 16) UCLK clock
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* ticks (in 1/16 steps).
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*/
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/* UBRCONx register */
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#define UC_FRAME_MAX_LEN 12 /* 1 start + 8 data + 1 par + 2 stop */
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#define UBRCON_JITTER_MASK 0x3
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#define UBRCON_JITTER_POS(bit) ((bit) << 1) /* 0..UC_FRAME_MAX_LEN-1 */
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#define UBRCON_JITTER_NONE 0 /* no jitter for this bit */
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#define UBRCON_JITTER_INC 1 /* increment 1/16 bit width */
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#define UBRCON_JITTER_UNUSED 2 /* does nothing */
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#define UBRCON_JITTER_DEC 3 /* decremet 1/16 bit width */
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/* Autobauding:
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*
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* Initial UABRSTAT is NOT_INIT, it goes to READY when either of
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* UCON_AUTOBR bits are enabled for the first time.
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*
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* Interrupts are enabled/disabled using UCON_AUTOBR_INT_BIT and
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* checked using UTRSTAT_AUTOBR_INT_BIT, writing this bit cleans the
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* interrupt.
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*
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* When UCON_AUTOBR_START_BIT is enabled, autobauding starts and the
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* hardware waits for a low pulse on RX line.
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*
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* Once autobauding is started, when a falling edge is detected on
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* the RX line, UABRSTAT changes to COUNTING status, an internal
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* counter starts incrementing at UCLK clock frequency. During
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* COUNTING state, UABRCNT reads as the value of the previous ABR
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* count, not the value of the current internal count.
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*
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* Count finish when a rising edge is detected on the line, at this
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* moment internal counter stops and it can be read using UABRCNT
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* register, UABRSTAT goes to READY, AUTOBR_START_BIT is disabled,
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* and an interrupt is raised if UCON_AUTOBR_INT_BIT is enabled.
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*/
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/* UABRSTAT register */
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#define UABRSTAT_STATUS_MASK 0x3
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#define UABRSTAT_STATUS_POS 0
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#define UABRSTAT_STATUS_NOT_INIT 0 /* initial status */
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#define UABRSTAT_STATUS_READY 1 /* machine is ready */
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#define UABRSTAT_STATUS_COUNTING 2 /* count in progress */
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/*
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* structs
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*/
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struct uartc
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{
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/* static configuration */
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const uint32_t baddr;
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/* private */
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struct uartc_port *port_l[UART_PORT_MAX];
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};
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struct uartc_port
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{
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/* static configuration */
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struct uartc * const uartc;
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const uint8_t id; /* port number */
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const uint8_t rx_trg; /* UFCON_RX_FIFO_TRG_xxx */
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const uint8_t tx_trg; /* UFCON_TX_FIFO_TRG_xxx */
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const uint8_t clksel; /* UFCON_CLKSEL_xxx */
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const uint32_t clkhz; /* UCLK (PCLK or ECLK) frequency */
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void (* const tx_cb) (int len); /* ISRs */
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void (* const rx_cb) (int len, char *data, char *err, uint32_t abr_cnt);
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/* private */
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uint32_t baddr;
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uint32_t utrstat_int_mask;
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bool abr_aborted;
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uint8_t rx_data[UART_FIFO_SIZE]; /* data buffer for rx_cb */
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uint8_t rx_err[UART_FIFO_SIZE]; /* error buffer for rx_cb */
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#ifdef UC8702_DEBUG
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uint32_t n_tx_bytes;
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uint32_t n_rx_bytes;
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uint32_t n_ovr_err;
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uint32_t n_parity_err;
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uint32_t n_frame_err;
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uint32_t n_break_detect;
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uint32_t n_abnormal0;
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uint32_t n_abnormal1;
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#endif
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};
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/*
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* uc8702 low level API
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*/
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/* Initialization */
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void uartc_open(struct uartc* uartc);
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void uartc_close(struct uartc* uartc);
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void uartc_port_open(struct uartc_port *port);
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void uartc_port_close(struct uartc_port *port);
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void uartc_port_rx_onoff(struct uartc_port *port, bool onoff);
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void uartc_port_tx_onoff(struct uartc_port *port, bool onoff);
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/* Configuration */
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void uartc_port_config(struct uartc_port *port, unsigned int speed,
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uint8_t data_bits, uint8_t parity, uint8_t stop_bits);
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void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed);
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void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode);
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void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode);
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/* Transmit */
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bool uartc_port_tx_ready(struct uartc_port *port);
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void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch);
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void uartc_port_send_byte(struct uartc_port *port, uint8_t ch);
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/* Receive */
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bool uartc_port_rx_ready(struct uartc_port *port);
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uint8_t uartc_port_rx_byte(struct uartc_port *port);
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uint8_t uartc_port_read_byte(struct uartc_port *port);
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/* Autobauding */
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void uartc_port_abr_start(struct uartc_port *port);
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void uartc_port_abr_stop(struct uartc_port *port);
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/* ISR */
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void uartc_callback(struct uartc *uartc, int dev);
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#ifdef UC8702_DEBUG
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enum {
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ABR_INFO_ST_IDLE,
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ABR_INFO_ST_LAUNCHED,
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ABR_INFO_ST_COUNTING,
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ABR_INFO_ST_ABNORMAL
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};
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void uartc_port_get_line_info(struct uartc_port *port,
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int *tx_status, int *rx_status,
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int *tx_speed, int *rx_speed, char *line_cfg);
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int uartc_port_get_abr_info(struct uartc_port *port, unsigned int *abr_cnt);
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#endif
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#endif /* __UC8702_H__ */
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