478 lines
15 KiB
C
478 lines
15 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Andy Young
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <string.h>
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#include "config.h"
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#include "logf.h"
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#include "system.h"
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#include "kernel.h"
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#include "audio.h"
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#include "debug.h"
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#include "udacodec.h"
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#include "audiohw.h"
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/* The UDA1380 requires a clock signal at a multiple of the sample rate
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(256Fs, 384Fs, 512Fs or 768Fs, where Fs = sample rate).
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Some targets are able to supply this clock directly to the SYSCLK input.
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The H100 and H300 coldfire targets are limited in the selection of
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frequencies for this clock signal so they use a PLL inside the UDA1380
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(called the WSPLL) to regenerate it from the LRCK signal off the IIS bus.
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*/
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES)
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#define USE_WSPLL
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#endif
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/* convert tenth of dB volume (-840..0) to master volume register value */
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static int vol_tenthdb2hw(int db)
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{
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if (db < -720) /* 1.5 dB steps */
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return (2940 - db) / 15;
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else if (db < -660) /* 0.75 dB steps */
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return (1110 - db) * 2 / 15;
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else if (db < -520) /* 0.5 dB steps */
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return (520 - db) / 5;
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else /* 0.25 dB steps */
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return -db * 2 / 5;
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}
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/* convert tenth of dB volume (-780..0) to mixer volume register value */
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static int mixer_tenthdb2hw(int db)
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{
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if (db < -660) /* 1.5 dB steps */
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return (2640 - db) / 15;
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else if (db < -600) /* 0.75 dB steps */
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return (990 - db) * 2 / 15;
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else if (db < -460) /* 0.5 dB steps */
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return (460 - db) / 5;
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else /* 0.25 dB steps */
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return -db * 2 / 5;
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}
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/* ------------------------------------------------- */
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/* Local functions and variables */
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/* ------------------------------------------------- */
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static int uda1380_write_reg(unsigned char reg, unsigned short value);
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static unsigned short uda1380_regs[0x30];
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static short recgain_mic;
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static short recgain_line;
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#ifdef USE_WSPLL
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/* Internal control of WSPLL */
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static bool wspll_enable = false;
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static void wspll_on(bool on)
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{
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uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK);
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uda1380_regs[REG_PWR] &= ~PON_PLL;
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unsigned short pll_ena = (on) ? (ADC_CLK | DAC_CLK) : 0;
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unsigned short pll_pow = (on) ? PON_PLL : 0;
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uda1380_write_reg(REG_0, uda1380_regs[REG_0] | pll_ena);
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | pll_pow);
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wspll_enable = on;
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}
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#endif
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/* Definition of a playback configuration to start with */
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#define NUM_DEFAULT_REGS 13
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static const unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
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{
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REG_0, EN_DAC | EN_INT | EN_DEC | WSPLL_25_50 | SYSCLK_256FS,
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REG_I2S, I2S_IFMT_IIS,
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REG_PWR, PON_BIAS,
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/* PON_HP & PON_DAC is enabled later */
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REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
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/* 00=max, 3f=mute */
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REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
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/* 00=max, ff=mute */
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REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
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/* 00=max, ff=mute */
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REG_EQ, EQ_MODE_MAX,
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/* Bass and treble = 0 dB */
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REG_MUTE, MUTE_MASTER | MUTE_CH2,
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/* Mute everything to start with */
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REG_MIX_CTL, MIX_CTL_MIX | OVERSAMPLE_MODE(3),
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/* Enable mixer and 4x oversampling */
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REG_DEC_VOL, 0,
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REG_PGA, MUTE_ADC,
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REG_ADC, SKIP_DCFIL,
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REG_AGC, 0
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};
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/* Returns 0 if register was written or -1 if write failed */
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static int uda1380_write_reg(unsigned char reg, unsigned short value)
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{
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if (udacodec_write(reg, value) < 0)
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{
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DEBUGF("uda1380 error reg=0x%x", reg);
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return -1;
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}
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uda1380_regs[reg] = value;
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return 0;
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}
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/**
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* Sets left and right master volume (0(max) to 252(muted))
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*/
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void audiohw_set_volume(int vol_l, int vol_r)
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{
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vol_l = vol_tenthdb2hw(vol_l);
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vol_r = vol_tenthdb2hw(vol_r);
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uda1380_write_reg(REG_MASTER_VOL,
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MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
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}
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/**
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* Sets the bass value (0-12)
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*/
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void audiohw_set_bass(int value)
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{
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uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK)
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| BASSL(value) | BASSR(value));
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}
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/**
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* Sets the treble value (0-3)
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*/
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void audiohw_set_treble(int value)
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{
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uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK)
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| TREBLEL(value) | TREBLER(value));
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}
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static void audiohw_mute(bool mute)
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{
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unsigned int value = uda1380_regs[REG_MUTE];
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if (mute)
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value = value | MUTE_MASTER;
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else
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value = value & ~MUTE_MASTER;
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uda1380_write_reg(REG_MUTE, value);
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}
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/* Returns 0 if successful or -1 if some register failed */
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static int audiohw_set_regs(void)
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{
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int i;
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memset(uda1380_regs, 0, sizeof(uda1380_regs));
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/* Initialize all registers */
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for (i=0; i<NUM_DEFAULT_REGS; i++)
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{
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unsigned char reg = uda1380_defaults[i*2+0];
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unsigned short value = uda1380_defaults[i*2+1];
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if (uda1380_write_reg(reg, value) == -1)
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return -1;
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}
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return 0;
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}
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/**
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* Sets frequency settings for DAC and ADC relative to MCLK
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*
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* Selection for frequency ranges:
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* Fs: range: with:
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* 11025: 0 = 6.25 to 12.5 MCLK/2 SCLK, LRCK: Audio Clk / 16
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* 22050: 1 = 12.5 to 25 MCLK/2 SCLK, LRCK: Audio Clk / 8
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* 44100: 2 = 25 to 50 MCLK SCLK, LRCK: Audio Clk / 4 (default)
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* 88200: 3 = 50 to 100 MCLK SCLK, LRCK: Audio Clk / 2
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*/
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void audiohw_set_frequency(int fsel)
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{
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static const unsigned short values_reg[HW_NUM_FREQ][2] =
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{
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[HW_FREQ_11] = /* Fs: */
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{
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0,
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WSPLL_625_125 | SYSCLK_512FS
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},
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[HW_FREQ_22] =
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{
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0,
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WSPLL_125_25 | SYSCLK_256FS
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},
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[HW_FREQ_44] =
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{
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MIX_CTL_SEL_NS,
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WSPLL_25_50 | SYSCLK_256FS
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},
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HW_HAVE_88_([HW_FREQ_88] =
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{
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MIX_CTL_SEL_NS,
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WSPLL_50_100 | SYSCLK_256FS
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},)
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};
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const unsigned short *ent;
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if ((unsigned)fsel >= HW_NUM_FREQ)
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fsel = HW_FREQ_DEFAULT;
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ent = values_reg[fsel];
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#ifdef USE_WSPLL
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/* Enable WSPLL if needed (for Iriver H100 and H300 series) */
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HW_HAVE_88_(
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if (fsel == HW_FREQ_88)
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{
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/* Only at this case we need use WSPLL on DAC part for Iriver H100 and H300 series, because Coldfire work
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at 11289600 Hz frequency and SYSCLK of UDA1380 can only be 256fs, 384fs, 512fs and 768fs. But in this case SYSCLK
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is 128fs : 11289600 / 88200 = 128 */
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if (!wspll_enable) wspll_on(true);
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}
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else
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)
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{
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/* At this case WSPLL clock and SYSCLK has same value and we don't use WSPLL to avoid WSPLL errors */
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if (wspll_enable) wspll_on(false);
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}
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#endif
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/* Set WSPLL input frequency range or SYSCLK divider */
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uda1380_regs[REG_0] &= ~0xf;
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uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ent[1]);
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/* Choose 3rd order or 5th order noise shaper */
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uda1380_regs[REG_MIX_CTL] &= ~MIX_CTL_SEL_NS;
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uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | ent[0]);
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}
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/* Initialize UDA1380 codec with default register values (uda1380_defaults) */
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void audiohw_init(void)
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{
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recgain_mic = 0;
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recgain_line = 0;
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udacodec_reset();
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if (audiohw_set_regs() == -1)
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{
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/* this shoud never (!) happen. */
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logf("uda1380: audiohw_init failed");
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}
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}
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void audiohw_postinit(void)
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{
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/* Sleep a while so the power can stabilize (especially a long
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delay is needed for the line out connector). */
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sleep(HZ);
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/* Power on FSDAC and HP amp. */
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
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/* UDA1380: Unmute the master channel
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(DAC should be at zero point now). */
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audiohw_mute(false);
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}
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void audiohw_set_prescaler(int val)
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{
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val = mixer_tenthdb2hw(-val);
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uda1380_write_reg(REG_MIX_VOL,
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MIX_VOL_CH_1(val) | MIX_VOL_CH_2(val));
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}
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/* Nice shutdown of UDA1380 codec */
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void audiohw_close(void)
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{
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/* First enable mute and sleep a while */
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uda1380_write_reg(REG_MUTE, MUTE_MASTER);
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sleep(HZ/8);
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/* Then power off the rest of the chip */
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uda1380_write_reg(REG_PWR, 0);
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uda1380_write_reg(REG_0, 0); /* Disable codec */
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}
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/**
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* Calling this function enables the UDA1380 to send
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* sound samples over the I2S bus, which is connected
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* to the processor's IIS1 interface.
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*
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* source_mic: true=record from microphone, false=record from line-in (or radio)
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*/
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void audiohw_enable_recording(bool source_mic)
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{
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#ifdef USE_WSPLL
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if (wspll_enable) uda1380_regs[REG_0] &= ~(ADC_CLK | DAC_CLK);
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#endif
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uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
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if (source_mic)
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{
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/* VGA_GAIN: 0=0 dB, F=30dB */
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/* Output of left ADC is fed into right bitstream */
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uda1380_regs[REG_PWR] &= ~(PON_PGAR | PON_ADCR);
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
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uda1380_regs[REG_ADC] &= ~SKIP_DCFIL;
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uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK)
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| SEL_LNA | SEL_MIC | EN_DCFIL);
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uda1380_write_reg(REG_PGA, 0);
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}
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else
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{
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/* PGA_GAIN: 0=0 dB, F=24dB */
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uda1380_regs[REG_PWR] &= ~PON_LNA;
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL
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| PON_PGAR | PON_ADCR);
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uda1380_write_reg(REG_ADC, EN_DCFIL);
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uda1380_write_reg(REG_PGA, uda1380_regs[REG_PGA] & PGA_GAIN_MASK);
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}
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sleep(HZ/8);
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uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
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uda1380_write_reg(REG_MIX_CTL, MIX_MODE(1));
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}
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/**
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* Stop sending samples on the I2S bus
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*/
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void audiohw_disable_recording(void)
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{
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uda1380_write_reg(REG_PGA, MUTE_ADC);
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sleep(HZ/8);
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uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
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uda1380_regs[REG_PWR] &= ~(PON_LNA | PON_ADCL | PON_ADCR |
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PON_PGAL | PON_PGAR);
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uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR]);
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uda1380_regs[REG_0] &= ~EN_ADC;
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#ifdef USE_WSPLL
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if (wspll_enable) uda1380_write_reg(REG_0, uda1380_regs[REG_0] | ADC_CLK | DAC_CLK);
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#endif
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uda1380_write_reg(REG_ADC, SKIP_DCFIL);
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}
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/**
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* Set recording gain and volume
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*
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* type: params: ranges:
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* AUDIO_GAIN_MIC: left -128 .. 108 -> -64 .. 54 dB gain
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* AUDIO_GAIN_LINEIN left & right -128 .. 96 -> -64 .. 48 dB gain
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*
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* Note: - For all types the value 0 gives 0 dB gain.
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* - order of setting both values determines if the small glitch will
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be a peak or a dip. The small glitch is caused by the time between
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setting the two gains
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*/
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void audiohw_set_recvol(int left, int right, int type)
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{
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int left_ag, right_ag;
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switch (type)
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{
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case AUDIO_GAIN_MIC:
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left_ag = MIN(MAX(0, left / 4), 15);
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left -= left_ag * 4;
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if(left < recgain_mic)
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{
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uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
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| DEC_VOLR(left));
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uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
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& ~VGA_GAIN_MASK)
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| VGA_GAIN(left_ag));
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}
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else
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{
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uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
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& ~VGA_GAIN_MASK)
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| VGA_GAIN(left_ag));
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uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
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| DEC_VOLR(left));
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}
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recgain_mic = left;
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logf("Mic: %dA/%dD", left_ag, left);
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break;
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case AUDIO_GAIN_LINEIN:
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left_ag = MIN(MAX(0, left / 6), 8);
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left -= left_ag * 6;
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right_ag = MIN(MAX(0, right / 6), 8);
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right -= right_ag * 6;
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if(left < recgain_line)
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{
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/* for this order we can combine both registers,
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making the glitch even smaller */
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unsigned short value_dec;
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unsigned short value_pga;
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value_dec = DEC_VOLL(left) | DEC_VOLR(right);
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value_pga = (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK)
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| PGA_GAINL(left_ag) | PGA_GAINR(right_ag);
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if (udacodec_write2(REG_DEC_VOL, value_dec, value_pga) < 0)
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{
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DEBUGF("uda1380 error reg=combi rec gain");
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}
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else
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{
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uda1380_regs[REG_DEC_VOL] = value_dec;
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uda1380_regs[REG_PGA] = value_pga;
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}
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}
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else
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{
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uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA]
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& ~PGA_GAIN_MASK)
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| PGA_GAINL(left_ag)
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| PGA_GAINR(right_ag));
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uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
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| DEC_VOLR(right));
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}
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recgain_line = left;
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logf("Line L: %dA/%dD", left_ag, left);
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logf("Line R: %dA/%dD", right_ag, right);
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break;
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}
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}
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/**
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* Enable or disable recording monitor (so one can listen to the recording)
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*
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*/
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void audiohw_set_monitor(bool enable)
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{
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if (enable) /* enable channel 2 */
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uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);
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else /* mute channel 2 */
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uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] | MUTE_CH2);
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}
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