2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
114 lines
5 KiB
C
114 lines
5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "kernel.h"
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#include "system.h"
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#include "power.h"
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#include "timer.h"
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/* Settings for all possible clock frequencies (with properly working timers)
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* NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that!
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*
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* xxx_REFRESH_TIMER below
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* system.h, CPUFREQ_xxx_MULT |
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* | |
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* V V
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* PLLCR & Rftim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT ~0x70400000 16MB CSCR0 CS2Pre CS2Post CS2Wait
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* -----------------------------------------------------------------
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* 11289600 1 0x00800200 4 0x0180 1 1 0
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* 22579200 2 0x0589e025 10 0x0180 1 1 0
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* 33868800 3 0x0388e025 15 0x0180 1 1 0
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* 45158400 4 0x0589e021 21 0x0580 1 1 0
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* 56448000 5 0x0289e025 26 0x0580 2 1 0
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* 67737600 6 0x0388e021 32 0x0980 2 1 0
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* 79027200 7 0x038a6021 37 0x0980 2 1 0
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* 90316800 8 0x038be021 43 0x0d80 2 1 0
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* 101606400 9 0x01892025 48 0x0d80 2 1 0
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* 112896000 10 0x0189e025 54 0x1180 3 1 0
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* 124185600 11 0x018ae025 59 0x1180 3 1 1
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*/
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 21
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#define DEFAULT_REFRESH_TIMER 4
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency(long frequency)
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#else
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void cf_set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void cf_set_cpu_frequency(long frequency)
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#endif
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{
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switch(frequency)
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{
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case CPUFREQ_MAX:
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DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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PLLCR = 0x018ae025 | (PLLCR & 0x70400000);
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x100000 | (1 << 13) | (3 << 10);
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/* SBUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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break;
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case CPUFREQ_NORMAL:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
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/* BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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default:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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/* Power down PLL, but keep CRSEL and CLSEL */
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PLLCR = 0x00800200 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
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/* BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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}
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}
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