acb0917556
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30264 a1c6a512-1295-4272-9138-f99709370657
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
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#include "nsf_emu.h"
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#ifndef NSF_EMU_APU_ONLY
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#include "nes_namco_apu.h"
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#include "nes_fds_apu.h"
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#include "nes_mmc5_apu.h"
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#endif
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#include "blargg_source.h"
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int Cpu_read( struct Nsf_Emu* this, nes_addr_t addr )
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{
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int result = this->cpu.low_mem [addr & 0x7FF];
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if ( addr & 0xE000 )
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{
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result = *Cpu_get_code( &this->cpu, addr );
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if ( addr < sram_addr )
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{
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if ( addr == status_addr )
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result = Apu_read_status( &this->apu, Cpu_time( &this->cpu ) );
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else
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{
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#ifndef NSF_EMU_APU_ONLY
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if ( namco_enabled( this ) && addr == namco_data_reg_addr )
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return Namco_read_data( &this->namco );
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if ( fds_enabled( this ) && (unsigned) (addr - fds_io_addr) < fds_io_size )
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return Fds_read( &this->fds, Cpu_time( &this->cpu ), addr );
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if ( mmc5_enabled( this ) ) {
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int i = addr - 0x5C00;
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if ( (unsigned) i < mmc5_exram_size )
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return this->mmc5.exram [i];
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int m = addr - 0x5205;
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if ( (unsigned) m < 2 )
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return (this->mmc5_mul [0] * this->mmc5_mul [1]) >> (m * 8) & 0xFF;
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}
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#endif
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result = addr >> 8; // simulate open bus
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}
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}
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}
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/* if ( addr != 0x2002 )
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debug_printf( "Read unmapped $%.4X\n", (unsigned) addr ); */
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return result;
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}
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void Cpu_write( struct Nsf_Emu* this, nes_addr_t addr, int data )
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{
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int offset = addr - sram_addr;
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if ( (unsigned) offset < sram_size )
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{
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this->sram [offset] = data;
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}
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else
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{
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// after sram because cpu handles most low_ram accesses internally already
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int temp = addr & (low_ram_size-1); // also handles wrap-around
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if ( !(addr & 0xE000) )
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{
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this->cpu.low_mem [temp] = data;
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}
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else
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{
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int bank = addr - banks_addr;
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if ( (unsigned) bank < bank_count )
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{
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Write_bank( this, bank, data );
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}
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else if ( (unsigned) (addr - start_addr) <= end_addr - start_addr )
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{
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Apu_write_register( &this->apu, Cpu_time( &this->cpu ), addr, data );
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}
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else
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{
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#ifndef NSF_EMU_APU_ONLY
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// 0x8000-0xDFFF is writable
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int i = addr - 0x8000;
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if ( fds_enabled( this ) && (unsigned) i < fdsram_size )
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fdsram( this ) [i] = data;
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else
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#endif
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Cpu_write_misc( this, addr, data );
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}
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}
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}
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}
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#define CPU_READ( emu, addr, time ) Cpu_read( emu, addr )
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#define CPU_WRITE( emu, addr, data, time ) Cpu_write( emu, addr, data )
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