91f9350cbd
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5296 a1c6a512-1295-4272-9138-f99709370657
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "lcd.h"
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#include "sh7034.h"
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#include "kernel.h"
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#include "thread.h"
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#include "debug.h"
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#include "system.h"
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#ifdef CONFIG_TUNER
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/* Signals:
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DI (Data In) - PB0 (doubles as data pin for the LCD)
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CL (Clock) - PB1 (doubles as clock for the LCD)
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CE (Chip Enable) - PB3 (also chip select for the LCD, but active low)
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DO (Data Out) - PB4
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*/
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/* cute little functions */
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#define CE_LO and_b(~0x08, PBDRL_ADDR)
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#define CE_HI or_b(0x08, PBDRL_ADDR)
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#define CL_LO and_b(~0x02, PBDRL_ADDR)
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#define CL_HI or_b(0x02, PBDRL_ADDR)
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#define DO (PBDR & 0x10)
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#define DI_LO and_b(~0x01, PBDRL_ADDR)
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#define DI_HI or_b(0x01, PBDRL_ADDR)
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#define START or_b((0x08 | 0x02), PBDRL_ADDR)
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/* delay loop */
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#define DELAY do { int _x; for(_x=0;_x<10;_x++);} while (0)
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int fmradio_read(int addr)
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{
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int i;
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int data = 0;
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START;
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/* First address bit */
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CL_LO;
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if(addr & 2)
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DI_HI;
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else
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DI_LO;
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DELAY;
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CL_HI;
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DELAY;
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/* Second address bit */
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CL_LO;
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if(addr & 1)
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DI_HI;
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else
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DI_LO;
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DELAY;
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CL_HI;
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DELAY;
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for(i = 0; i < 21;i++)
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{
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CL_LO;
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DELAY;
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data <<= 1;
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data |= (DO)?1:0;
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CL_HI;
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DELAY;
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}
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CE_LO;
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return data;
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}
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void fmradio_set(int addr, int data)
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{
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int i;
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/* Include the address in the data */
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data |= addr << 21;
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START;
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for(i = 0; i < 23;i++)
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{
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CL_LO;
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DELAY;
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if(data & (1 << 22))
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DI_HI;
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else
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DI_LO;
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data <<= 1;
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CL_HI;
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DELAY;
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}
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CE_LO;
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}
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#endif
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