ad375c0bbc
This caused mounting of µSD to fail on Fuzev2 in some cases, although the card is detected properly This might be the cause of playback glitches (more frequent for lossless files) on clipv2 Trying to set the main PLL at 384MHz and FCLK at 240MHz didn't work, so there might be some problems not understood yet git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26979 a1c6a512-1295-4272-9138-f99709370657
245 lines
10 KiB
C
245 lines
10 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef CLOCK_TARGET_H
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#define CLOCK_TARGET_H
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#include "config.h"
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#include "cpu.h"
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/* returns clock divider, given maximal target frequency and clock reference */
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#define CLK_DIV(ref, target) ((ref + target - 1) / target)
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/* Frequency and Bus Settings
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* These bus settings work on the assumption that unboosted performance will be
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* based on fastbus mode(FCLK == PCLK) at a frequency configured with this file.
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* Boosted performance defaults to synchronous bus but will be changed to
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* asynchronous bus if FCLK is not an integer multiple of PCLK.
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* The player starts up in fastbus mode and synchronous or asynchronous mode is
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* implemented in the set_cpu_frequency() function in system-as3525.c. There
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* are limitations on both frequencies and frequency relationships listed in 7.3.14
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* of the as3525 datasheet that need to be observed. If you are determined to
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* use a frequency that is not "legal" you can do that. There are no checks for
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* legal frequency values, only some validity checks to make sure the divider
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* value fits into the number of bits allotted to it.
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*
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* The CLOCK_DIV macro does a pretty good job at selecting divider values but
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* you can always override it by choosing your own value and commenting out the
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* macro. AS3525_FCLK_PREDIV values other than 0 allow you to choose frequencies
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* from lines below the main PLL frequency lines. AS3525_FCLK_POSTDIV
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* will be calculated automagically depending on the value you have selected
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* for AS3525_FCLK_FREQ. You may add more PLL frequencies by simply commenting
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* out the current #defines for AS3525_PLLA_FREQ & AS3525_PLLA_SETTING and
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* adding a #define for FREQ and divider setting to produce that frequency.I
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* have included USB & PLLB for future use but commented them out for now.
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*/
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/* Clock Sources */
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#define AS3525_CLK_MAIN 0
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#define AS3525_CLK_PLLA 1
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#define AS3525_CLK_PLLB 2
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#define AS3525_CLK_FCLK 3 /* Available as PCLK input only */
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/** ************ Change these to reconfigure clocking scheme *******************/
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#if CONFIG_CPU == AS3525v2
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/* PLLA & PLLB registers differ from AS3525(v1)
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* PLL bits:
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* - bit 0-6 = F-1 (F=multiplier)
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* - bit 7-9 = R-1 (R=divisor)
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* - bit 10 = OD (output divider)? Divides by 2 if set.
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* - bit 11 = unknown (no effect)
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* - bit 12 = unknown (always set to 1)
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* Fpll = Fin * F / (R * OD), where Fin = 12 MHz
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*/
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#define AS3525_PLLA_FREQ 240000000
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#define AS3525_PLLA_SETTING 0x113B
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#define AS3525_PLLB_FREQ 192000000
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#define AS3525_PLLB_SETTING 0x155F
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#define AS3525_FCLK_PREDIV 0
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#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ
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/* XXX: CGU_PERI might also be different (i.e. no PCLK_DIV1_SEL), so we don't
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* set bit 6 (PCLK_DIV1_SEL) for the moment
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*
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* Note that setting bits 1:0 have no effect and they always read back as 0
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* Also note that CGU_PERI is based on fclk, not PLLA
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*/
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#ifdef SANSA_FUZEV2
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/* display is unbearably slow at 24MHz
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* 34285715 HZ works ok but 40MHz works even better*/
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#define AS3525_DRAM_FREQ 40000000 /* Initial DRAM frequency */
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#else
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#define AS3525_DRAM_FREQ 24000000 /* Initial DRAM frequency */
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#endif /* SANSA_FUZEV2 */
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#else
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/* AS3525v1 */
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/* PLL frequencies and settings*/
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#define AS3525_PLLA_FREQ 248000000 /*124,82.7,62,49.6,41.3,35.4 */
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/* FCLK_PREDIV-> *7/8 = 217MHz 108.5 ,72.3, 54.25, 43.4, 36.17 */
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/* *6/8 = 186MHz 93, 62, 46.5, 37.2 */
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/* *5/8 = 155MHz 77.5, 51.67, 38.75 */
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#define AS3525_PLLA_SETTING 0x261F
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/* PLLB frequencies and settings (audio and USB) */
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#define AS3525_PLLB_FREQ 384000000 /* allows 44.1kHz with 0.04% error*/
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#define AS3525_PLLB_SETTING 0x2630
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//#define AS3525_PLLA_FREQ 384000000 /*192,128,96,76.8,64,54.9,48,42.7,38.4*/
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/* FCLK_PREDIV-> *7/8 = 336MHz 168, 112, 84, 67.2, 56, 48, 42, 37.3*/
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/* *6/8 = 288MHz 144, 96, 72, 57.6, 48, 41.1, */
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/* *5/8 = 240MHz 120, 80, 60, 48, 40 */
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//#define AS3525_PLLA_SETTING 0x2630
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#define AS3525_FCLK_PREDIV 0 /* div = (8-n)/8 Enter manually & postdiv will be calculated*/
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/* 0 gives you the PLLA 1st line choices, 1 the 2nd line etc. */
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#define AS3525_FCLK_FREQ 248000000 /* Boosted FCLK frequency */
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#define AS3525_DRAM_FREQ 62000000 /* Initial DRAM frequency */
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/* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
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#endif /* CONFIG_CPU == AS3525v2 */
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#define AS3525_PCLK_FREQ (AS3525_DRAM_FREQ/1) /* PCLK divided from DRAM freq */
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#define AS3525_DBOP_FREQ (AS3525_PCLK_FREQ/1) /* DBOP divided from PCLK freq */
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/** ****************************************************************************/
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/* Tell the software what frequencies we're running */
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#define CPUFREQ_MAX AS3525_FCLK_FREQ
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#define CPUFREQ_DEFAULT AS3525_PCLK_FREQ
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#define CPUFREQ_NORMAL AS3525_PCLK_FREQ
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/* FCLK */
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#define AS3525_FCLK_SEL AS3525_CLK_PLLA
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#define AS3525_FCLK_POSTDIV (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), AS3525_FCLK_FREQ) - 1) /*div=1/(n+1)*/
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#if CONFIG_CPU == AS3525v2
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/* On as3525v2 we change fclk by writing to CGU_PROC */
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#define AS3525_FCLK_POSTDIV_UNBOOSTED (CLK_DIV((AS3525_PLLA_FREQ*(8-AS3525_FCLK_PREDIV)/8), CPUFREQ_NORMAL) - 1) /*div=1/(n+1) */
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/* Since pclk is based on fclk, we need to change CGU_PERI as well */
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#define AS3525_PCLK_DIV0_UNBOOSTED (CLK_DIV(CPUFREQ_NORMAL, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
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#endif /* CONFIG_CPU == AS3525v2 */
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/* MCLK */
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#define AS3525_MCLK_SEL AS3525_CLK_PLLA
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#if (AS3525_MCLK_SEL==AS3525_CLK_PLLA)
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#define AS3525_MCLK_FREQ AS3525_PLLA_FREQ
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#elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB)
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#define AS3525_MCLK_FREQ AS3525_PLLB_FREQ
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#else
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#error Choose either PLLA or PLLB for MCLK!
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#endif
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/* PCLK */
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/* Figure out if we need to use asynchronous bus */
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#if ((CONFIG_CPU == AS3525) && (AS3525_FCLK_FREQ % AS3525_PCLK_FREQ))
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#define ASYNCHRONOUS_BUS /* Boosted mode asynchronous */
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#endif
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#ifdef ASYNCHRONOUS_BUS
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#define AS3525_PCLK_SEL AS3525_CLK_PLLA /* PLLA input for asynchronous */
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#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_PLLA_FREQ, AS3525_DRAM_FREQ) - 1)/*div=1/(n+1)*/
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#else /* ASYNCHRONOUS_BUS */
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#define AS3525_PCLK_SEL AS3525_CLK_FCLK /* Fclk input for synchronous */
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#define AS3525_PCLK_DIV0 (CLK_DIV(AS3525_FCLK_FREQ, AS3525_DRAM_FREQ) - 1) /*div=1/(n+1)*/
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#endif /* ASYNCHRONOUS_BUS */
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/*unable to use AS3525_PCLK_DIV1 != 0 successfuly so far*/
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#define AS3525_PCLK_DIV1 (CLK_DIV(AS3525_DRAM_FREQ, AS3525_PCLK_FREQ) - 1)/* div = 1/(n+1)*/
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/* PCLK as Source */
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#define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
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#define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
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#define AS3525_I2C_FREQ 400000
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#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
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#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
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#define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
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#define AS3525_SSP_FREQ 12000000
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#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
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#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
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#if CONFIG_CPU == AS3525v2
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#define AS3525_MS_FREQ 120000000
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#define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1)
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#define AS3525_SDSLOT_FREQ 24000000
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#define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1)
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#define AS3525_IDE_FREQ 80000000
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#else
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#define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */
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#endif /* CONFIG_CPU == AS3525v2 */
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//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */
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//#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/
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/* Validity Checks */
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/* AS3525_PCLK_FREQ */
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#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
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#error PCLK frequency is too low : clock divider will not fit !
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#endif
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/* AS3525_DBOP_FREQ */
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#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
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#error DBOP frequency is too low : clock divider will not fit !
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#endif
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/* AS3525_IDE_FREQ */
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#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
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#error IDE frequency is too low : clock divider will not fit !
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#endif
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/* AS3525_I2C_FREQ */
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#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
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#error I2C frequency is too low : clock divider will not fit !
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#endif
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/* AS3525_SSP_FREQ */
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#if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
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#error SSP frequency is too low : clock divider will not fit !
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#endif
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/* AS3525_SD_IDENT_FREQ */
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#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
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#error SD IDENTIFICATION frequency is too low : clock divider will not fit !
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#endif
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/* I2SIN / I2SOUT frequencies */
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/* low samplerate */
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#if ((AS3525_MCLK_FREQ/(128*8000))) > 512 /* 8kHz = lowest frequency */
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#error AS3525_MCLK_FREQ is too high for 8kHz samplerate !
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#endif
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/* high samplerate */
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#if ((AS3525_MCLK_FREQ/(128*96000))) < 1 /* 96kHz = highest frequency */
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#error AS3525_MCLK_FREQ is too low for 96kHz samplerate !
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#endif
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#endif /* CLOCK_TARGET_H */
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