ad0a0569ea
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22920 a1c6a512-1295-4272-9138-f99709370657
217 lines
6 KiB
C
217 lines
6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#ifdef IPOD_NANO2G
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#include "ftl-target.h"
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#endif
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(EXT0);
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default_interrupt(EXT1);
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default_interrupt(EXT2);
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default_interrupt(EINT_VBUS);
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default_interrupt(EINTG);
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default_interrupt(INT_TIMERA);
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default_interrupt(INT_WDT);
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default_interrupt(INT_TIMERB);
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default_interrupt(INT_TIMERC);
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default_interrupt(INT_TIMERD);
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default_interrupt(INT_DMA);
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default_interrupt(INT_ALARM_RTC);
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default_interrupt(INT_PRI_RTC);
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default_interrupt(RESERVED1);
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default_interrupt(INT_UART);
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default_interrupt(INT_USB_HOST);
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default_interrupt(INT_USB_FUNC);
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default_interrupt(INT_LCDC_0);
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default_interrupt(INT_LCDC_1);
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default_interrupt(INT_ECC);
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default_interrupt(INT_CALM);
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default_interrupt(INT_ATA);
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default_interrupt(INT_UART0);
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default_interrupt(INT_SPDIF_OUT);
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default_interrupt(INT_SDCI);
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default_interrupt(INT_LCD);
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default_interrupt(INT_SPI);
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default_interrupt(INT_IIC);
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default_interrupt(RESERVED2);
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default_interrupt(INT_MSTICK);
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default_interrupt(INT_ADC_WAKEUP);
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default_interrupt(INT_ADC);
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#if CONFIG_CPU==S5L8701
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static void (* const irqvector[])(void) =
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{ /* still 90% unverified and probably incorrect */
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EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERB,INT_WDT,INT_TIMERA,
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INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
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INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
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INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
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};
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#else
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static void (* const irqvector[])(void) =
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{
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EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
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INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
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INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
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INT_SDCI,INT_LCD,INT_SPI,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
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};
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#endif
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#if CONFIG_CPU==S5L8701
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static const char * const irqname[] =
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{ /* still 90% unverified and probably incorrect */
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"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERB","INT_WDT","INT_TIMERA",
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"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
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"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC",
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"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
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};
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#else
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static const char * const irqname[] =
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{
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"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
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"INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
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"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
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"INT_SDCI","INT_LCD","INT_SPI","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
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};
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#endif
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static void UIRQ(void)
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{
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unsigned int offset = INTOFFSET;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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int irq_no = INTOFFSET;
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irqvector[irq_no]();
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/* clear interrupt */
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SRCPND = (1 << irq_no);
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INTPND = INTPND;
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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static void gpio_init(void)
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{
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}
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static void clock_init(void)
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{
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}
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void system_init(void)
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{
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}
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void system_reboot(void)
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{
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#ifdef IPODNANO2G
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if (ftl_sync() != 0) panicf("Failed to unmount flash!");
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/* Reset the SoC */
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asm volatile(" \
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msr CPSR_c, #0xd3 \
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mov r5, #0x110000 \
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add r5, r5, #0xff \
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add r6, r5, #0xa00 \
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mov r10, #0x3c800000 \
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str r6, [r10] \
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mov r6, #0xff0 \
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str r6, [r10,#4] \
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str r5, [r10]")
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/* Wait for reboot to kick in */
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while(1);
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#endif
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}
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void system_exception_wait(void)
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{
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while (1);
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if (cpu_frequency == frequency)
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return;
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/* CPU/COP frequencies can be scaled between Fbus (min) and Fsys (max).
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Fbus should not be set below ~32Mhz with LCD enabled or the display
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will be garbled. */
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if (frequency == CPUFREQ_MAX)
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{
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}
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else if (frequency == CPUFREQ_NORMAL)
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{
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}
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else
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{
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}
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asm volatile (
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"nop \n\t"
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"nop \n\t"
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"nop \n\t"
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);
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cpu_frequency = frequency;
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}
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#endif
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