dfe46436b1
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24547 a1c6a512-1295-4272-9138-f99709370657
165 lines
4.3 KiB
ArmAsm
165 lines
4.3 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* Arm bootloader and startup code based on startup.s from the iPodLinux loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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.global start
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start:
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msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifndef CREATIVE_ZVx
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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#endif
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/* Disable data and instruction cache, high vectors (at 0xffff0000 instead of 0x00000000) */
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mrc p15, 0, r0, c1, c0, 0
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/* clear bits 13, 9:8 (--VI --RS) */
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bic r0, r0, #0x00003300
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/* clear bits 7, 2:0 (B--- -C-M) */
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bic r0, r0, #0x00000085
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/* make sure bit 2 (A) Align is set */
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orr r0, r0, #0x00000002
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mcr p15, 0, r0, c1, c0, 0
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#if !defined(STUB)
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#ifndef CREATIVE_ZVx
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#endif
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#endif /* !STUB */
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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bsszero:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi bsszero
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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stackmunge:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi stackmunge
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2 /* IRQ disabled, FIQ enabled */
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */
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ldr sp, =fiq_stack
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/* Let abort and undefined modes use IRQ stack */
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msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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/* Switch to supervisor mode (no IRQ) */
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msr cpsr_c, #0xd3
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ldr sp, =stackend
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start_loc:
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bl main
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/* main() should never return */
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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.section .vectors,"aw"
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b start
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b undef_instr_handler
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b software_int_handler
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b prefetch_abort_handler
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b data_abort_handler
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b reserved_handler
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b irq_handler
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b fiq_handler
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.text
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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we're in. Second parameter is exception number, used for a string lookup
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in UIE.
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*/
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undef_instr_handler:
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sub r0, lr, #4
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mov r1, #0
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b UIE
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/* We run supervisor mode most of the time, and should never see a software
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exception being thrown. Perhaps make it illegal and call UIE?
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*/
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software_int_handler:
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reserved_handler:
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movs pc, lr
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prefetch_abort_handler:
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sub r0, lr, #4
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mov r1, #1
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b UIE
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data_abort_handler:
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sub r0, lr, #8
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mov r1, #2
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b UIE
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#ifdef STUB
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UIE:
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b UIE
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#endif
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