f890bd504f
Change-Id: I9dae85eb27337154ddb82015666773a5254cc388
105 lines
4.9 KiB
C
105 lines
4.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.8
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* XML versions: stmp3600:2.3.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__MEMCPY__H__
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#define __HEADERGEN__STMP3600__MEMCPY__H__
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#define REGS_MEMCPY_BASE (0x80014000)
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#define REGS_MEMCPY_VERSION "2.3.0"
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/**
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* Register: HW_MEMCPY_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_MEMCPY_CTRL (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x0))
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#define HW_MEMCPY_CTRL_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x4))
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#define HW_MEMCPY_CTRL_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0x8))
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#define HW_MEMCPY_CTRL_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x0 + 0xc))
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#define BP_MEMCPY_CTRL_SFTRST 31
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#define BM_MEMCPY_CTRL_SFTRST 0x80000000
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#define BV_MEMCPY_CTRL_SFTRST__RUN 0x0
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#define BV_MEMCPY_CTRL_SFTRST__RESET 0x1
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#define BF_MEMCPY_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BF_MEMCPY_CTRL_SFTRST_V(v) ((BV_MEMCPY_CTRL_SFTRST__##v << 31) & 0x80000000)
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#define BP_MEMCPY_CTRL_CLKGATE 30
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#define BM_MEMCPY_CTRL_CLKGATE 0x40000000
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#define BV_MEMCPY_CTRL_CLKGATE__RUN 0x0
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#define BV_MEMCPY_CTRL_CLKGATE__NO_CLKS 0x1
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#define BF_MEMCPY_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BF_MEMCPY_CTRL_CLKGATE_V(v) ((BV_MEMCPY_CTRL_CLKGATE__##v << 30) & 0x40000000)
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#define BP_MEMCPY_CTRL_PRESENT 29
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#define BM_MEMCPY_CTRL_PRESENT 0x20000000
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#define BV_MEMCPY_CTRL_PRESENT__UNAVAILABLE 0x0
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#define BV_MEMCPY_CTRL_PRESENT__AVAILABLE 0x1
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#define BF_MEMCPY_CTRL_PRESENT(v) (((v) << 29) & 0x20000000)
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#define BF_MEMCPY_CTRL_PRESENT_V(v) ((BV_MEMCPY_CTRL_PRESENT__##v << 29) & 0x20000000)
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#define BP_MEMCPY_CTRL_BURST 16
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#define BM_MEMCPY_CTRL_BURST 0x10000
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#define BF_MEMCPY_CTRL_BURST(v) (((v) << 16) & 0x10000)
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#define BP_MEMCPY_CTRL_XFER_SIZE 0
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#define BM_MEMCPY_CTRL_XFER_SIZE 0xffff
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#define BF_MEMCPY_CTRL_XFER_SIZE(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_MEMCPY_DATA
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* Address: 0x10
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* SCT: yes
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*/
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#define HW_MEMCPY_DATA (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x0))
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#define HW_MEMCPY_DATA_SET (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x4))
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#define HW_MEMCPY_DATA_CLR (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0x8))
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#define HW_MEMCPY_DATA_TOG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x10 + 0xc))
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#define BP_MEMCPY_DATA_DATA 0
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#define BM_MEMCPY_DATA_DATA 0xffffffff
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#define BF_MEMCPY_DATA_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_MEMCPY_DEBUG
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* Address: 0x20
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* SCT: no
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*/
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#define HW_MEMCPY_DEBUG (*(volatile unsigned long *)(REGS_MEMCPY_BASE + 0x20))
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#define BP_MEMCPY_DEBUG_DST_END_CMD 30
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#define BM_MEMCPY_DEBUG_DST_END_CMD 0x40000000
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#define BF_MEMCPY_DEBUG_DST_END_CMD(v) (((v) << 30) & 0x40000000)
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#define BP_MEMCPY_DEBUG_DST_KICK 29
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#define BM_MEMCPY_DEBUG_DST_KICK 0x20000000
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#define BF_MEMCPY_DEBUG_DST_KICK(v) (((v) << 29) & 0x20000000)
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#define BP_MEMCPY_DEBUG_DST_DMA_REQ 28
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#define BM_MEMCPY_DEBUG_DST_DMA_REQ 0x10000000
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#define BF_MEMCPY_DEBUG_DST_DMA_REQ(v) (((v) << 28) & 0x10000000)
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#define BP_MEMCPY_DEBUG_SRC_KICK 25
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#define BM_MEMCPY_DEBUG_SRC_KICK 0x2000000
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#define BF_MEMCPY_DEBUG_SRC_KICK(v) (((v) << 25) & 0x2000000)
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#define BP_MEMCPY_DEBUG_SRC_DMA_REQ 24
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#define BM_MEMCPY_DEBUG_SRC_DMA_REQ 0x1000000
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#define BF_MEMCPY_DEBUG_SRC_DMA_REQ(v) (((v) << 24) & 0x1000000)
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#define BP_MEMCPY_DEBUG_WRITE_STATE 2
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#define BM_MEMCPY_DEBUG_WRITE_STATE 0xc
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#define BF_MEMCPY_DEBUG_WRITE_STATE(v) (((v) << 2) & 0xc)
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#define BP_MEMCPY_DEBUG_READ_STATE 0
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#define BM_MEMCPY_DEBUG_READ_STATE 0x3
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#define BF_MEMCPY_DEBUG_READ_STATE(v) (((v) << 0) & 0x3)
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#endif /* __HEADERGEN__STMP3600__MEMCPY__H__ */
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