284 lines
13 KiB
C
284 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.8
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* XML versions: stmp3600:2.4.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__EMI__H__
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#define __HEADERGEN__STMP3600__EMI__H__
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#define REGS_EMI_BASE (0x80020000)
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#define REGS_EMI_VERSION "2.4.0"
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/**
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* Register: HW_EMI_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0))
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#define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4))
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#define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8))
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#define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc))
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#define BP_EMI_CTRL_SFTRST 31
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#define BM_EMI_CTRL_SFTRST 0x80000000
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#define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BP_EMI_CTRL_CLKGATE 30
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#define BM_EMI_CTRL_CLKGATE 0x40000000
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#define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BP_EMI_CTRL_CE3_MODE 3
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#define BM_EMI_CTRL_CE3_MODE 0x8
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#define BV_EMI_CTRL_CE3_MODE__STATIC 0x0
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#define BV_EMI_CTRL_CE3_MODE__DRAM 0x1
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#define BF_EMI_CTRL_CE3_MODE(v) (((v) << 3) & 0x8)
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#define BF_EMI_CTRL_CE3_MODE_V(v) ((BV_EMI_CTRL_CE3_MODE__##v << 3) & 0x8)
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#define BP_EMI_CTRL_CE2_MODE 2
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#define BM_EMI_CTRL_CE2_MODE 0x4
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#define BV_EMI_CTRL_CE2_MODE__STATIC 0x0
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#define BV_EMI_CTRL_CE2_MODE__DRAM 0x1
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#define BF_EMI_CTRL_CE2_MODE(v) (((v) << 2) & 0x4)
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#define BF_EMI_CTRL_CE2_MODE_V(v) ((BV_EMI_CTRL_CE2_MODE__##v << 2) & 0x4)
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#define BP_EMI_CTRL_CE1_MODE 1
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#define BM_EMI_CTRL_CE1_MODE 0x2
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#define BV_EMI_CTRL_CE1_MODE__STATIC 0x0
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#define BV_EMI_CTRL_CE1_MODE__DRAM 0x1
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#define BF_EMI_CTRL_CE1_MODE(v) (((v) << 1) & 0x2)
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#define BF_EMI_CTRL_CE1_MODE_V(v) ((BV_EMI_CTRL_CE1_MODE__##v << 1) & 0x2)
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#define BP_EMI_CTRL_CE0_MODE 0
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#define BM_EMI_CTRL_CE0_MODE 0x1
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#define BV_EMI_CTRL_CE0_MODE__STATIC 0x0
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#define BV_EMI_CTRL_CE0_MODE__DRAM 0x1
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#define BF_EMI_CTRL_CE0_MODE(v) (((v) << 0) & 0x1)
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#define BF_EMI_CTRL_CE0_MODE_V(v) ((BV_EMI_CTRL_CE0_MODE__##v << 0) & 0x1)
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/**
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* Register: HW_EMI_STAT
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* Address: 0x10
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* SCT: no
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*/
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#define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10))
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#define BP_EMI_STAT_DRAM_PRESENT 31
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#define BM_EMI_STAT_DRAM_PRESENT 0x80000000
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#define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000)
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#define BP_EMI_STAT_STATIC_PRESENT 30
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#define BM_EMI_STAT_STATIC_PRESENT 0x40000000
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#define BF_EMI_STAT_STATIC_PRESENT(v) (((v) << 30) & 0x40000000)
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#define BP_EMI_STAT_LARGE_DRAM_ENABLED 29
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#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000
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#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000)
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#define BP_EMI_STAT_WRITE_BUFFER_DATA 1
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#define BM_EMI_STAT_WRITE_BUFFER_DATA 0x2
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#define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY 0x0
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#define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY 0x1
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#define BF_EMI_STAT_WRITE_BUFFER_DATA(v) (((v) << 1) & 0x2)
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#define BF_EMI_STAT_WRITE_BUFFER_DATA_V(v) ((BV_EMI_STAT_WRITE_BUFFER_DATA__##v << 1) & 0x2)
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#define BP_EMI_STAT_BUSY 0
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#define BM_EMI_STAT_BUSY 0x1
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#define BV_EMI_STAT_BUSY__NOT_BUSY 0x0
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#define BV_EMI_STAT_BUSY__BUSY 0x1
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#define BF_EMI_STAT_BUSY(v) (((v) << 0) & 0x1)
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#define BF_EMI_STAT_BUSY_V(v) ((BV_EMI_STAT_BUSY__##v << 0) & 0x1)
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/**
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* Register: HW_EMI_DEBUG
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* Address: 0x20
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* SCT: no
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*/
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#define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20))
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#define BP_EMI_DEBUG_STATIC_STATE 16
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#define BM_EMI_DEBUG_STATIC_STATE 0x70000
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#define BF_EMI_DEBUG_STATIC_STATE(v) (((v) << 16) & 0x70000)
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#define BP_EMI_DEBUG_DRAM_STATE 0
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#define BM_EMI_DEBUG_DRAM_STATE 0x1f
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#define BF_EMI_DEBUG_DRAM_STATE(v) (((v) << 0) & 0x1f)
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/**
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* Register: HW_EMI_DRAMSTAT
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* Address: 0x80
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* SCT: no
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*/
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#define HW_EMI_DRAMSTAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80))
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#define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK 2
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#define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK 0x4
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#define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) (((v) << 2) & 0x4)
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#define BP_EMI_DRAMSTAT_BUSY 1
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#define BM_EMI_DRAMSTAT_BUSY 0x2
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#define BF_EMI_DRAMSTAT_BUSY(v) (((v) << 1) & 0x2)
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#define BP_EMI_DRAMSTAT_READY 0
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#define BM_EMI_DRAMSTAT_READY 0x1
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#define BF_EMI_DRAMSTAT_READY(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_EMI_DRAMCTRL
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* Address: 0x90
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* SCT: yes
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*/
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#define HW_EMI_DRAMCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x0))
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#define HW_EMI_DRAMCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x4))
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#define HW_EMI_DRAMCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x8))
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#define HW_EMI_DRAMCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0xc))
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#define BP_EMI_DRAMCTRL_EMICLK_DIVIDE 24
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#define BM_EMI_DRAMCTRL_EMICLK_DIVIDE 0x7000000
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#define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v) (((v) << 24) & 0x7000000)
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#define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE 23
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#define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE 0x800000
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#define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) (((v) << 23) & 0x800000)
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#define BP_EMI_DRAMCTRL_EMICLK_ENABLE 21
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#define BM_EMI_DRAMCTRL_EMICLK_ENABLE 0x200000
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#define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v) (((v) << 21) & 0x200000)
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#define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE 20
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#define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE 0x100000
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#define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v) (((v) << 20) & 0x100000)
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#define BP_EMI_DRAMCTRL_DRAM_TYPE 16
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#define BM_EMI_DRAMCTRL_DRAM_TYPE 0xf0000
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#define BF_EMI_DRAMCTRL_DRAM_TYPE(v) (((v) << 16) & 0xf0000)
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#define BP_EMI_DRAMCTRL_PRECHARGE 2
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#define BM_EMI_DRAMCTRL_PRECHARGE 0x4
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#define BF_EMI_DRAMCTRL_PRECHARGE(v) (((v) << 2) & 0x4)
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#define BP_EMI_DRAMCTRL_SELF_REFRESH 1
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#define BM_EMI_DRAMCTRL_SELF_REFRESH 0x2
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#define BF_EMI_DRAMCTRL_SELF_REFRESH(v) (((v) << 1) & 0x2)
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/**
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* Register: HW_EMI_DRAMADDR
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* Address: 0xa0
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* SCT: yes
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*/
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#define HW_EMI_DRAMADDR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x0))
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#define HW_EMI_DRAMADDR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x4))
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#define HW_EMI_DRAMADDR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x8))
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#define HW_EMI_DRAMADDR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0xc))
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#define BP_EMI_DRAMADDR_MODE 8
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#define BM_EMI_DRAMADDR_MODE 0x100
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#define BV_EMI_DRAMADDR_MODE__RBC 0x0
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#define BV_EMI_DRAMADDR_MODE__BRC 0x1
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#define BF_EMI_DRAMADDR_MODE(v) (((v) << 8) & 0x100)
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#define BF_EMI_DRAMADDR_MODE_V(v) ((BV_EMI_DRAMADDR_MODE__##v << 8) & 0x100)
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#define BP_EMI_DRAMADDR_ROW_BITS 4
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#define BM_EMI_DRAMADDR_ROW_BITS 0xf0
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#define BF_EMI_DRAMADDR_ROW_BITS(v) (((v) << 4) & 0xf0)
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#define BP_EMI_DRAMADDR_COLUMN_BITS 0
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#define BM_EMI_DRAMADDR_COLUMN_BITS 0xf
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#define BF_EMI_DRAMADDR_COLUMN_BITS(v) (((v) << 0) & 0xf)
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/**
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* Register: HW_EMI_DRAMMODE
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* Address: 0xb0
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* SCT: no
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*/
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#define HW_EMI_DRAMMODE (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0))
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#define BP_EMI_DRAMMODE_CAS_LATENCY 4
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#define BM_EMI_DRAMMODE_CAS_LATENCY 0x70
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0 0x0
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1 0x1
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#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2 0x2
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#define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3 0x3
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4 0x4
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5 0x5
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6 0x6
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#define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7 0x7
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#define BF_EMI_DRAMMODE_CAS_LATENCY(v) (((v) << 4) & 0x70)
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#define BF_EMI_DRAMMODE_CAS_LATENCY_V(v) ((BV_EMI_DRAMMODE_CAS_LATENCY__##v << 4) & 0x70)
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/**
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* Register: HW_EMI_DRAMTIME
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* Address: 0xc0
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* SCT: yes
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*/
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#define HW_EMI_DRAMTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x0))
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#define HW_EMI_DRAMTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x4))
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#define HW_EMI_DRAMTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x8))
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#define HW_EMI_DRAMTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0xc))
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#define BP_EMI_DRAMTIME_TRFC 24
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#define BM_EMI_DRAMTIME_TRFC 0xf000000
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#define BF_EMI_DRAMTIME_TRFC(v) (((v) << 24) & 0xf000000)
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#define BP_EMI_DRAMTIME_TRC 20
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#define BM_EMI_DRAMTIME_TRC 0xf00000
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#define BF_EMI_DRAMTIME_TRC(v) (((v) << 20) & 0xf00000)
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#define BP_EMI_DRAMTIME_TRAS 16
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#define BM_EMI_DRAMTIME_TRAS 0xf0000
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#define BF_EMI_DRAMTIME_TRAS(v) (((v) << 16) & 0xf0000)
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#define BP_EMI_DRAMTIME_TRCD 12
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#define BM_EMI_DRAMTIME_TRCD 0xf000
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#define BF_EMI_DRAMTIME_TRCD(v) (((v) << 12) & 0xf000)
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#define BP_EMI_DRAMTIME_TRP 8
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#define BM_EMI_DRAMTIME_TRP 0x300
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#define BF_EMI_DRAMTIME_TRP(v) (((v) << 8) & 0x300)
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#define BP_EMI_DRAMTIME_TXSR 4
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#define BM_EMI_DRAMTIME_TXSR 0xf0
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#define BF_EMI_DRAMTIME_TXSR(v) (((v) << 4) & 0xf0)
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#define BP_EMI_DRAMTIME_REFRESH_COUNTER 0
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#define BM_EMI_DRAMTIME_REFRESH_COUNTER 0xf
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#define BF_EMI_DRAMTIME_REFRESH_COUNTER(v) (((v) << 0) & 0xf)
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/**
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* Register: HW_EMI_DRAMTIME2
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* Address: 0xd0
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* SCT: yes
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*/
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#define HW_EMI_DRAMTIME2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x0))
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#define HW_EMI_DRAMTIME2_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x4))
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#define HW_EMI_DRAMTIME2_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x8))
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#define HW_EMI_DRAMTIME2_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0xc))
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#define BP_EMI_DRAMTIME2_PRECHARGE_COUNT 0
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#define BM_EMI_DRAMTIME2_PRECHARGE_COUNT 0xffff
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#define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_EMI_STATICCTRL
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* Address: 0x100
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* SCT: yes
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*/
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#define HW_EMI_STATICCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x0))
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#define HW_EMI_STATICCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x4))
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#define HW_EMI_STATICCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x8))
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#define HW_EMI_STATICCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0xc))
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#define BP_EMI_STATICCTRL_MEM_WIDTH 2
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#define BM_EMI_STATICCTRL_MEM_WIDTH 0x4
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#define BF_EMI_STATICCTRL_MEM_WIDTH(v) (((v) << 2) & 0x4)
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#define BP_EMI_STATICCTRL_WRITE_PROTECT 1
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#define BM_EMI_STATICCTRL_WRITE_PROTECT 0x2
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#define BF_EMI_STATICCTRL_WRITE_PROTECT(v) (((v) << 1) & 0x2)
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#define BP_EMI_STATICCTRL_RESET_OUT 0
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#define BM_EMI_STATICCTRL_RESET_OUT 0x1
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#define BF_EMI_STATICCTRL_RESET_OUT(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_EMI_STATICTIME
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* Address: 0x110
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* SCT: yes
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*/
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#define HW_EMI_STATICTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x0))
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#define HW_EMI_STATICTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x4))
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#define HW_EMI_STATICTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x8))
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#define HW_EMI_STATICTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0xc))
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#define BP_EMI_STATICTIME_THZ 24
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#define BM_EMI_STATICTIME_THZ 0xf000000
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#define BF_EMI_STATICTIME_THZ(v) (((v) << 24) & 0xf000000)
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#define BP_EMI_STATICTIME_TDH 16
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#define BM_EMI_STATICTIME_TDH 0xf0000
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#define BF_EMI_STATICTIME_TDH(v) (((v) << 16) & 0xf0000)
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#define BP_EMI_STATICTIME_TDS 8
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#define BM_EMI_STATICTIME_TDS 0xf00
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#define BF_EMI_STATICTIME_TDS(v) (((v) << 8) & 0xf00)
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#define BP_EMI_STATICTIME_TAS 0
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#define BM_EMI_STATICTIME_TAS 0xf
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#define BF_EMI_STATICTIME_TAS(v) (((v) << 0) & 0xf)
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#endif /* __HEADERGEN__STMP3600__EMI__H__ */
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