a8c1fb55a4
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9309 a1c6a512-1295-4272-9138-f99709370657
82 lines
3.5 KiB
C
82 lines
3.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#include "kernel.h"
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#include "system.h"
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#include "power.h"
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#include "timer.h"
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 21
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#define DEFAULT_REFRESH_TIMER 4
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency(long frequency)
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{
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switch(frequency)
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{
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case CPUFREQ_MAX:
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DCR = (0x8200 | DEFAULT_REFRESH_TIMER);
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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PLLCR = 0x13042045;
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00000980; /* LCD: 2 wait states */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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break;
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case CPUFREQ_NORMAL:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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PLLCR = 0x16030045;
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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This may take up to 10ms! */
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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default:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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}
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}
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