db392245e2
Rework the irq code, to put more code in the C part. When interrupt nesting is enable, Rockbox gets pretty unstable so disable it for now. Change-Id: Iee18b539c80ea408273f6082975faaa87d3ee1b6
274 lines
8.7 KiB
C
274 lines
8.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2012 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "icoll-imx233.h"
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#include "rtc-imx233.h"
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#include "kernel-imx233.h"
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#include "string.h"
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#include "timrot-imx233.h"
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#define default_interrupt(name) \
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extern __attribute__((weak, alias("UIRQ"))) void name(void)
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static void UIRQ (void) __attribute__((interrupt ("IRQ")));
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void irq_handler(void) __attribute__((naked));
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void fiq_handler(void) __attribute__((interrupt("FIQ")));
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default_interrupt(INT_USB_CTRL);
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default_interrupt(INT_TIMER0);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_TIMER3);
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default_interrupt(INT_SSP1_DMA);
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default_interrupt(INT_SSP1_ERROR);
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default_interrupt(INT_I2C_DMA);
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default_interrupt(INT_I2C_ERROR);
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default_interrupt(INT_GPIO0);
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default_interrupt(INT_GPIO1);
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default_interrupt(INT_GPIO2);
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default_interrupt(INT_VDD5V);
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default_interrupt(INT_LRADC_CH0);
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default_interrupt(INT_LRADC_CH1);
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default_interrupt(INT_LRADC_CH2);
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default_interrupt(INT_LRADC_CH3);
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default_interrupt(INT_LRADC_CH4);
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default_interrupt(INT_LRADC_CH5);
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default_interrupt(INT_LRADC_CH6);
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default_interrupt(INT_LRADC_CH7);
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default_interrupt(INT_DAC_DMA);
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default_interrupt(INT_DAC_ERROR);
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default_interrupt(INT_ADC_DMA);
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default_interrupt(INT_ADC_ERROR);
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default_interrupt(INT_TOUCH_DETECT);
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default_interrupt(INT_RTC_1MSEC);
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/* STMP3700+ specific */
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#if IMX233_SUBTARGET >= 3700
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default_interrupt(INT_SSP2_DMA);
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default_interrupt(INT_SSP2_ERROR);
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default_interrupt(INT_DCP);
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default_interrupt(INT_LCDIF_DMA);
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default_interrupt(INT_LCDIF_ERROR);
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#endif
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/* STMP3780+ specific */
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#if IMX233_SUBTARGET >= 3780
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#endif
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default_interrupt(INT_SOFTWARE0);
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default_interrupt(INT_SOFTWARE1);
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default_interrupt(INT_SOFTWARE2);
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default_interrupt(INT_SOFTWARE3);
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typedef void (*isr_t)(void);
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static isr_t isr_table[INT_SRC_COUNT] =
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{
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[INT_SRC_USB_CTRL] = INT_USB_CTRL,
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[INT_SRC_TIMER(0)] = INT_TIMER0,
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[INT_SRC_TIMER(1)] = INT_TIMER1,
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[INT_SRC_TIMER(2)] = INT_TIMER2,
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[INT_SRC_TIMER(3)] = INT_TIMER3,
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[INT_SRC_SSP1_DMA] = INT_SSP1_DMA,
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[INT_SRC_SSP1_ERROR] = INT_SSP1_ERROR,
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[INT_SRC_I2C_DMA] = INT_I2C_DMA,
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[INT_SRC_I2C_ERROR] = INT_I2C_ERROR,
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[INT_SRC_GPIO0] = INT_GPIO0,
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[INT_SRC_GPIO1] = INT_GPIO1,
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[INT_SRC_GPIO2] = INT_GPIO2,
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[INT_SRC_VDD5V] = INT_VDD5V,
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[INT_SRC_LRADC_CHx(0)] = INT_LRADC_CH0,
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[INT_SRC_LRADC_CHx(1)] = INT_LRADC_CH1,
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[INT_SRC_LRADC_CHx(2)] = INT_LRADC_CH2,
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[INT_SRC_LRADC_CHx(3)] = INT_LRADC_CH3,
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[INT_SRC_LRADC_CHx(4)] = INT_LRADC_CH4,
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[INT_SRC_LRADC_CHx(5)] = INT_LRADC_CH5,
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[INT_SRC_LRADC_CHx(6)] = INT_LRADC_CH6,
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[INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7,
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[INT_SRC_DAC_DMA] = INT_DAC_DMA,
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[INT_SRC_DAC_ERROR] = INT_DAC_ERROR,
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[INT_SRC_ADC_DMA] = INT_ADC_DMA,
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[INT_SRC_ADC_ERROR] = INT_ADC_ERROR,
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[INT_SRC_TOUCH_DETECT] = INT_TOUCH_DETECT,
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[INT_SRC_RTC_1MSEC] = INT_RTC_1MSEC,
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#if IMX233_SUBTARGET >= 3700
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[INT_SRC_SSP2_DMA] = INT_SSP2_DMA,
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[INT_SRC_SSP2_ERROR] = INT_SSP2_ERROR,
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[INT_SRC_DCP] = INT_DCP,
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[INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA,
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[INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR,
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#endif
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#if IMX233_SUBTARGET >= 3780
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#endif
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[INT_SRC_SOFTWARE(0)] = INT_SOFTWARE0,
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[INT_SRC_SOFTWARE(1)] = INT_SOFTWARE1,
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[INT_SRC_SOFTWARE(2)] = INT_SOFTWARE2,
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[INT_SRC_SOFTWARE(3)] = INT_SOFTWARE3,
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};
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#define IRQ_STORM_DELAY 100 /* ms */
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#define IRQ_STORM_THRESHOLD 100000 /* allows irq / delay */
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static uint32_t irq_count_old[INT_SRC_COUNT];
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static uint32_t irq_count[INT_SRC_COUNT];
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unsigned imx233_icoll_get_priority(int src)
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{
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#if IMX233_SUBTARGET < 3780
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return BF_RDn(ICOLL_PRIORITYn, src / 4, PRIORITYx(src % 4));
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#else
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return BF_RDn(ICOLL_INTERRUPTn, src, PRIORITY);
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#endif
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}
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struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src)
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{
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struct imx233_icoll_irq_info_t info;
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#if IMX233_SUBTARGET < 3780
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info.enabled = BF_RDn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
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#else
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info.enabled = BF_RDn(ICOLL_INTERRUPTn, src, ENABLE);
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#endif
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info.priority = imx233_icoll_get_priority(src);
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info.freq = irq_count_old[src];
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return info;
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}
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static void do_irq_stat(void)
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{
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imx233_keep_alive();
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static unsigned counter = 0;
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if(counter++ >= HZ)
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{
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counter = 0;
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memcpy(irq_count_old, irq_count, sizeof(irq_count));
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memset(irq_count, 0, sizeof(irq_count));
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}
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}
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static void UIRQ(void)
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{
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panicf("Unhandled IRQ %02X",
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(unsigned int)(HW_ICOLL_VECTOR - (uint32_t)isr_table) / 4);
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}
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/* return the priority level */
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void _irq_handler(void)
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{
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/* read vector and notify as side effect */
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uint32_t vec = HW_ICOLL_VECTOR;
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int irq_nr = (vec - HW_ICOLL_VBASE) / 4;
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/* check for IRQ storm */
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if(irq_count[irq_nr]++ > IRQ_STORM_THRESHOLD)
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panicf("IRQ %d: storm detected", irq_nr);
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/* do some regular stat */
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if(irq_nr == INT_SRC_TIMER(TIMER_TICK))
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do_irq_stat();
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/* enable interrupts again */
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//enable_irq();
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/* process interrupt */
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(*(isr_t *)vec)();
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/* acknowledge completion of IRQ */
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HW_ICOLL_LEVELACK = 1 << imx233_icoll_get_priority(irq_nr);
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}
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void irq_handler(void)
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{
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/* save stuff */
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asm volatile(
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"sub lr, lr, #4 \n" /* Create return address */
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"stmfd sp!, { r0-r5, r12, lr } \n" /* Save what gets clobbered */
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"ldr r1, =0x8001c290 \n" /* Save pointer to instruction */
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"str lr, [r1] \n" /* in HW_DIGCTL_SCRATCH0 */
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"mrs lr, spsr \n" /* Save SPSR_irq */
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"stmfd sp!, { r1, lr } \n" /* Push it on the stack */
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"msr cpsr_c, #0x93 \n" /* Switch to SVC mode, IRQ disabled */
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"mov r4, lr \n" /* Save lr_SVC */
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"and r5, sp, #4 \n" /* Align SVC stack */
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"sub sp, sp, r5 \n" /* on 8-byte boundary */
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"blx _irq_handler \n" /* Process IRQ */
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"add sp, sp, r5 \n" /* Undo alignement */
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"mov lr, r4 \n" /* Restore lr_SVC */
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"msr cpsr_c, #0x92 \n" /* Mask IRQ, return to IRQ mode */
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"ldmfd sp!, { r1, lr } \n" /* Reload saved value */
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"msr spsr_cxsf, lr \n" /* Restore SPSR_irq */
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"ldmfd sp!, { r0-r5, r12, pc }^ \n" /* Restore regs, and RFE */);
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}
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void fiq_handler(void)
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{
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}
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void imx233_icoll_force_irq(unsigned src, bool enable)
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{
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#if IMX233_SUBTARGET < 3780
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if(enable)
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BF_SETn(ICOLL_PRIORITYn, src / 4, SOFTIRQx(src % 4));
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else
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BF_CLRn(ICOLL_PRIORITYn, src / 4, SOFTIRQx(src % 4));
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#else
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if(enable)
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BF_SETn(ICOLL_INTERRUPTn, src, SOFTIRQ);
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else
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BF_CLRn(ICOLL_INTERRUPTn, src, SOFTIRQ);
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#endif
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}
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void imx233_icoll_enable_interrupt(int src, bool enable)
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{
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#if IMX233_SUBTARGET < 3780
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if(enable)
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BF_SETn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
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else
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BF_CLRn(ICOLL_PRIORITYn, src / 4, ENABLEx(src % 4));
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#else
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if(enable)
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BF_SETn(ICOLL_INTERRUPTn, src, ENABLE);
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else
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BF_CLRn(ICOLL_INTERRUPTn, src, ENABLE);
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#endif
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}
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void imx233_icoll_set_priority(int src, unsigned prio)
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{
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#if IMX233_SUBTARGET < 3780
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BF_WRn(ICOLL_PRIORITYn, src / 4, PRIORITYx(src % 4), prio);
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#else
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BF_WRn(ICOLL_INTERRUPTn, src, PRIORITY, prio);
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#endif
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}
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void imx233_icoll_init(void)
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{
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imx233_reset_block(&HW_ICOLL_CTRL);
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/* enable read side-effect mode for nested interrupts */
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BF_SET(ICOLL_CTRL, ARM_RSE_MODE);
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/* disable all interrupts */
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/* priority = 0, disable, disable fiq */
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#if IMX233_SUBTARGET >= 3780
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for(int i = 0; i < INT_SRC_COUNT; i++)
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HW_ICOLL_INTERRUPTn(i) = 0;
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#else
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for(int i = 0; i < INT_SRC_COUNT / 4; i++)
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HW_ICOLL_PRIORITYn(i) = 0;
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#endif
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/* setup vbase as isr_table */
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HW_ICOLL_VBASE = (uint32_t)&isr_table;
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/* enable final irq bit */
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BF_SET(ICOLL_CTRL, IRQ_FINAL_ENABLE);
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}
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