f33330c0ff
Remove the implementations of all exceptions handlers from the various crt0.S files and have a single implementation in system-arm.h The new implementation is weak so that it can be overwritten by some specific code (like the unwinder) Change-Id: Ib3e041ed6037376bbe0e79286057e1051640dd90 Reviewed-on: http://gerrit.rockbox.org/205 Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
171 lines
4.6 KiB
ArmAsm
171 lines
4.6 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .vectors,"ax",%progbits
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.code 32
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/* most handlers are in DRAM which is too far away for a relative jump */
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ldr pc, =start
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ldr pc, =undef_instr_handler
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ldr pc, =software_int_handler
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ldr pc, =prefetch_abort_handler
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ldr pc, =data_abort_handler
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ldr pc, =reserved_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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/* When starting, we will be running at 0x40000000 most probably
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* but the code is expected to be loaded at 0x4xxxxxxx (uncached) and to be
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* running at virtual address 0xyyyyyyyy (cached). So we first
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* need to move everything to the right locationn then we setup the mmu and
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* jump to the final virtual address. */
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.text
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.global start
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/** The code below must be able to run at any address **/
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start:
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/* Copy running address */
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sub r7, pc, #8
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/* Save r0 */
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mov r6, r0
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/* enter supervisor mode, disable IRQ/FIQ */
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msr cpsr_c, #0xd3
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/* Disable MMU, disable caching and buffering;
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* use low exception range address (the core uses high range by default) */
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, =0x3005
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bic r0, r1
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mcr p15, 0, r0, c1, c0, 0
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/* To call the C code we need a stack, since the stack is in virtual memory
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* use the stack's physical address */
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ldr sp, =stackend_phys
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/* Enable MMU */
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bl memory_init
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/* Copy the DRAM
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* Assume the dram binary blob is located at the loading address (r5) */
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mov r2, r7
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ldr r3, =_dramcopystart
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ldr r4, =_dramcopyend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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mov r2, #0
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mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache
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/* Jump to real location */
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ldr pc, =remap
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remap:
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/** The code below is be running at the right virtual address **/
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Copy the IRAM */
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/* must be done before bss is zeroed */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#ifdef HAVE_INIT_ATTR
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/* copy init data to codec buffer */
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/* must be done before bss is zeroed */
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ldr r2, =_initcopy
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ldr r3, =_initstart
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ldr r4, =_initend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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mov r2, #0
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mcr p15, 0, r2, c7, c5, 0 @ Invalidate ICache
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#endif
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =fiq_stack
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3
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ldr sp, =irq_stack
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msr cpsr_c, #0xd7
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb
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ldr sp, =irq_stack
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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ldr r2, =stackbegin
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ldr r3, =0xdeadbeef
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1:
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cmp sp, r2
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strhi r3, [r2], #4
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bhi 1b
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/* Jump to main */
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mov r0, r6
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mov r1, r7
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bl main
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1:
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b 1b
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/* 256 words of IRQ stack */
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.space 256*4
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irq_stack:
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/* 256 words of FIQ stack */
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.space 256*4
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fiq_stack:
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end:
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