7abf2b53a4
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657
45 lines
1.8 KiB
C
45 lines
1.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Michael Sevakis
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "i2s.h"
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void i2s_reset(void)
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{
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/* How SYSCLK for codec is derived (USBPLL=338.688MHz).
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*
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* SSI post dividers (SSI2 PODF=4, SSI2 PRE PODF=0):
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* 338688000Hz / 5 = 67737600Hz = ssi1_clk
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*
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* SSI bit clock dividers (DIV2=1, PSR=0, PM=0):
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* ssi1_clk / 4 = 16934400Hz = INT_BIT_CLK (MCLK)
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*
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* WM Codec post divider (MCLKDIV=1.5):
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* INT_BIT_CLK (MCLK) / 1.5 = 11289600Hz = 256*fs = SYSCLK
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*/
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imx31_regmod32(&CCM_PDR1,
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((1-1) << CCM_PDR1_SSI1_PRE_PODF_POS) |
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((5-1) << CCM_PDR1_SSI1_PODF_POS) |
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((8-1) << CCM_PDR1_SSI2_PRE_PODF_POS) |
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((64-1) << CCM_PDR1_SSI2_PODF_POS),
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CCM_PDR1_SSI1_PODF | CCM_PDR1_SSI2_PODF |
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CCM_PDR1_SSI1_PRE_PODF | CCM_PDR1_SSI2_PRE_PODF);
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}
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