2f5f2ba91d
Many imx233 targets boot in a very low performance mode, typically cpu and dram at 24MHz. This results in very slow boots and very unstable USB bootloader mode. Since cpu frequency scaling is disabled in bootloader in rockbox, always make the frequency scaling code available and boost at boot time. Change-Id: Ie96623c00f7c4cd9a377b84dcb14b772558cfa4d
309 lines
9.1 KiB
C
309 lines
9.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "gcc_extensions.h"
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#include "system-target.h"
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#include "cpu.h"
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#include "clkctrl-imx233.h"
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#include "pinctrl-imx233.h"
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#include "timrot-imx233.h"
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#include "dma-imx233.h"
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#include "ssp-imx233.h"
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#include "i2c-imx233.h"
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#if IMX233_SUBTARGET >= 3700
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#include "dcp-imx233.h"
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#endif
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#include "pwm-imx233.h"
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#include "icoll-imx233.h"
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#include "lradc-imx233.h"
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#include "rtc-imx233.h"
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#include "power-imx233.h"
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#include "emi-imx233.h"
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#include "lcd.h"
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#include "backlight-target.h"
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#include "button.h"
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#include "fmradio_i2c.h"
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#include "powermgmt.h"
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void imx233_chip_reset(void)
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{
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#if IMX233_SUBTARGET >= 3700
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HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP;
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#else
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HW_POWER_RESET = BF_OR2(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1));
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#endif
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}
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void system_reboot(void)
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{
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_backlight_off();
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disable_irq();
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/* use watchdog to reset */
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imx233_chip_reset();
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while(1);
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}
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void system_exception_wait(void)
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{
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/* make sure lcd and backlight are on */
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lcd_update();
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_backlight_on();
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_backlight_set_brightness(DEFAULT_BRIGHTNESS_SETTING);
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/* wait until button release (if a button is pressed) */
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#ifdef HAVE_BUTTON_DATA
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int data;
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while(button_read_device(&data));
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/* then wait until next button press */
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while(!button_read_device(&data));
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#else
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while(button_read_device());
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/* then wait until next button press */
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while(!button_read_device());
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#endif
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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static void set_page_tables(void)
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{
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/* map every memory region to itself */
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map_section(0, 0, 0x1000, CACHE_NONE);
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/* map RAM and enable caching for it */
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map_section(DRAM_ORIG, CACHED_DRAM_ADDR, MEMORYSIZE, CACHE_ALL);
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map_section(DRAM_ORIG, BUFFERED_DRAM_ADDR, MEMORYSIZE, BUFFERED);
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}
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void memory_init(void)
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{
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ttb_init();
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set_page_tables();
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enable_mmu();
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}
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void system_init(void)
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{
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/* NOTE: don't use anything here that might require tick task !
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* It is initialized by kernel_init *after* system_init().
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* The main() will naturally set cpu speed to normal after kernel_init()
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* so don't bother if the cpu is running at 24MHz here.
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* Make sure IO clock is running at expected speed */
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imx233_clkctrl_init();
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imx233_clkctrl_enable(CLK_PLL, true);
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#if IMX233_SUBTARGET >= 3700
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imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll
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#endif
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imx233_rtc_init();
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imx233_icoll_init();
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imx233_pinctrl_init();
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imx233_timrot_init();
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imx233_dma_init();
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imx233_ssp_init();
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#if IMX233_SUBTARGET >= 3700
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imx233_dcp_init();
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#endif
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imx233_pwm_init();
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imx233_lradc_init();
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imx233_power_init();
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imx233_i2c_init();
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imx233_powermgmt_init();
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/* make sure auto-slow is disable now, we don't know at which frequency we
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* are running and auto-slow could violate constraints on {xbus,hbus} */
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imx233_clkctrl_enable_auto_slow(false);
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imx233_clkctrl_set_auto_slow_div(BV_CLKCTRL_HBUS_SLOW_DIV__BY8);
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cpu_frequency = imx233_clkctrl_get_freq(CLK_CPU);
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#if CONFIG_TUNER
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fmradio_i2c_init();
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#endif
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}
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bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
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{
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uint32_t cur = HW_DIGCTL_MICROSECONDS;
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if(ref + us_delay <= ref)
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return !(cur > ref) && !(cur < (ref + us_delay));
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else
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return (cur < ref) || cur >= (ref + us_delay);
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}
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void imx233_reset_block(volatile uint32_t *block_reg)
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{
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/* deassert reset and clock gate */
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__REG_CLR(*block_reg) = __BLOCK_SFTRST;
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while(*block_reg & __BLOCK_SFTRST);
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__REG_CLR(*block_reg) = __BLOCK_CLKGATE;
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while(*block_reg & __BLOCK_CLKGATE);
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/* soft-reset */
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__REG_SET(*block_reg) = __BLOCK_SFTRST;
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/* make sure block is gated off */
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while(!(*block_reg & __BLOCK_CLKGATE));
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/* bring block out of reset */
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__REG_CLR(*block_reg) = __BLOCK_SFTRST;
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while(*block_reg & __BLOCK_SFTRST);
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/* make sure clock is running */
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__REG_CLR(*block_reg) = __BLOCK_CLKGATE;
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while(*block_reg & __BLOCK_CLKGATE);
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}
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void udelay(unsigned us)
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{
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uint32_t ref = HW_DIGCTL_MICROSECONDS;
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while(!imx233_us_elapsed(ref, us));
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}
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void imx233_digctl_set_arm_cache_timings(unsigned timings)
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{
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#if IMX233_SUBTARGET >= 3780
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HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings),
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DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
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#else
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HW_DIGCTL_ARMCACHE = BF_OR3(DIGCTL_ARMCACHE, ITAG_SS(timings),
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DTAG_SS(timings), CACHE_SS(timings));
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#endif
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}
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struct cpufreq_profile_t
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{
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/* key */
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long cpu_freq;
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/* parameters */
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int vddd, vddd_bo;
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int hbus_div;
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int cpu_idiv, cpu_fdiv;
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long emi_freq;
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int arm_cache_timings;
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};
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static struct cpufreq_profile_t cpu_profiles[] =
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{
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/* clk_p@454.74 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.550 V */
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{IMX233_CPUFREQ_454_MHz, 1550, 1450, 3, 1, 19, IMX233_EMIFREQ_130_MHz, 0},
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/* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.275 V */
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{IMX233_CPUFREQ_261_MHz, 1275, 1175, 2, 1, 33, IMX233_EMIFREQ_130_MHz, 0},
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/* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz, VDDD@1.050 V */
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{IMX233_CPUFREQ_64_MHz, 1050, 975, 1, 5, 27, IMX233_EMIFREQ_64_MHz, 0},
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/* dummy */
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{0, 0, 0, 0, 0, 0, 0, 0}
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};
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#define NR_CPU_PROFILES ((int)(sizeof(cpu_profiles)/sizeof(cpu_profiles[0])))
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void imx233_set_cpu_frequency(long frequency)
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{
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/* don't change the frequency if it is useless (changes are expensive) */
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if(cpu_frequency == frequency)
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return;
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struct cpufreq_profile_t *prof = cpu_profiles;
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while(prof->cpu_freq != 0 && prof->cpu_freq != frequency)
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prof++;
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if(prof->cpu_freq == 0)
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return;
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/* disable auto-slow (enable back afterwards) */
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imx233_clkctrl_enable_auto_slow(false);
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/* set VDDIO to the right value */
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imx233_power_set_regulator(REGULATOR_VDDIO, 3300, 3125);
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/* WARNING watch out the order ! */
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if(frequency > cpu_frequency)
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{
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/* Change VDDD regulator */
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imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
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/* Change ARM cache timings */
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imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
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/* Switch CPU to crystal at 24MHz */
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imx233_clkctrl_set_bypass(CLK_CPU, true);
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/* Program CPU divider for PLL */
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imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
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imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
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/* Change the HBUS divider to its final value */
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imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
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/* Switch back CPU to PLL */
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imx233_clkctrl_set_bypass(CLK_CPU, false);
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/* Set the new EMI frequency */
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imx233_emi_set_frequency(prof->emi_freq);
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}
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else
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{
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/* Switch CPU to crystal at 24MHz */
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imx233_clkctrl_set_bypass(CLK_CPU, true);
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/* Program HBUS divider to its final value */
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imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
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/* Program CPU divider for PLL */
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imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
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imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
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/* Switch back CPU to PLL */
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imx233_clkctrl_set_bypass(CLK_CPU, false);
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/* Set the new EMI frequency */
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imx233_emi_set_frequency(prof->emi_freq);
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/* Change ARM cache timings */
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imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
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/* Change VDDD regulator */
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imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
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}
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/* enable auto slow again */
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imx233_clkctrl_enable_auto_slow(true);
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/* update frequency */
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cpu_frequency = frequency;
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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return imx233_set_cpu_frequency(frequency);
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}
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#endif
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void imx233_enable_usb_controller(bool enable)
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{
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if(enable)
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BF_CLR(DIGCTL_CTRL, USB_CLKGATE);
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else
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BF_SET(DIGCTL_CTRL, USB_CLKGATE);
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}
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void imx233_enable_usb_phy(bool enable)
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{
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if(enable)
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{
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BF_CLR(USBPHY_CTRL, SFTRST);
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BF_CLR(USBPHY_CTRL, CLKGATE);
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HW_USBPHY_PWD_CLR = 0xffffffff;
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}
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else
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{
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HW_USBPHY_PWD_SET = 0xffffffff;
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BF_SET(USBPHY_CTRL, SFTRST);
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BF_SET(USBPHY_CTRL, CLKGATE);
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}
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}
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