298 lines
7.6 KiB
C
298 lines
7.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#include "sfc-x1000.h"
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#include "gpio-x1000.h"
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#include "irq-x1000.h"
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#include "x1000/sfc.h"
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#include "x1000/cpm.h"
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/* DMA works, but not in the SPL due to some hardware not being set up right.
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* Only the SPL and bootloader actually require flash access, so to keep it
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* simple, DMA is unconditionally disabled. */
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//#define NEED_SFC_DMA
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#if defined(BOOTLOADER_SPL)
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# if X1000_EXCLK_FREQ == 24000000
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# define FIXED_CLK_FREQ 600000000
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# define FIXED_CLK_SRC X1000_CLK_MPLL
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# elif X1000_EXCLK_FREQ == 26000000
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# define FIXED_CLK_FREQ 598000000
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# define FIXED_CLK_SRC X1000_CLK_MPLL
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# else
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# error "bad EXCLK freq"
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# endif
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#endif
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#define FIFO_THRESH 31
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#define SFC_STATUS_PENDING (-1)
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#ifdef NEED_SFC_DMA
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static struct mutex sfc_mutex;
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static struct semaphore sfc_sema;
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static struct timeout sfc_lockup_tmo;
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static bool sfc_inited = false;
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static volatile int sfc_status;
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#else
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# define sfc_status SFC_STATUS_OK
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#endif
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void sfc_init(void)
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{
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#ifdef NEED_SFC_DMA
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if(sfc_inited)
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return;
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mutex_init(&sfc_mutex);
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semaphore_init(&sfc_sema, 1, 0);
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sfc_inited = true;
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#endif
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}
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void sfc_lock(void)
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{
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#ifdef NEED_SFC_DMA
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mutex_lock(&sfc_mutex);
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#endif
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}
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void sfc_unlock(void)
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{
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#ifdef NEED_SFC_DMA
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mutex_unlock(&sfc_mutex);
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#endif
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}
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void sfc_open(void)
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{
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gpio_config(GPIO_A, 0x3f << 26, GPIO_DEVICE(1));
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jz_writef(CPM_CLKGR, SFC(0));
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jz_writef(SFC_GLB, OP_MODE_V(SLAVE), PHASE_NUM(1),
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THRESHOLD(FIFO_THRESH), WP_EN(1));
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REG_SFC_CGE = 0;
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REG_SFC_INTC = 0x1f;
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REG_SFC_MEM_ADDR = 0;
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#ifdef NEED_SFC_DMA
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jz_writef(SFC_GLB, OP_MODE_V(DMA), BURST_MD_V(INCR32));
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system_enable_irq(IRQ_SFC);
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#endif
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}
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void sfc_close(void)
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{
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#ifdef NEED_SFC_DMA
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system_disable_irq(IRQ_SFC);
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#endif
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REG_SFC_CGE = 0x1f;
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jz_writef(CPM_CLKGR, SFC(1));
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}
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void sfc_set_clock(x1000_clk_t clksrc, uint32_t freq)
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{
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uint32_t in_freq;
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#ifdef FIXED_CLK_FREQ
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/* Small optimization to save code space in SPL by not polling clock */
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clksrc = FIXED_CLK_SRC;
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in_freq = FIXED_CLK_FREQ;
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#else
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in_freq = clk_get(clksrc);
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#endif
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uint32_t div = clk_calc_div(in_freq, freq);
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jz_writef(CPM_SSICDR, CE(1), CLKDIV(div - 1),
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SFC_CS(clksrc == X1000_CLK_MPLL ? 1 : 0));
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while(jz_readf(CPM_SSICDR, BUSY));
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jz_writef(CPM_SSICDR, CE(0));
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}
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#ifdef NEED_SFC_DMA
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static int sfc_lockup_tmo_cb(struct timeout* tmo)
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{
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(void)tmo;
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int irq = disable_irq_save();
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if(sfc_status == SFC_STATUS_PENDING) {
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sfc_status = SFC_STATUS_LOCKUP;
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jz_overwritef(SFC_TRIG, STOP(1));
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semaphore_release(&sfc_sema);
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}
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restore_irq(irq);
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return 0;
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}
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static void sfc_wait_end(void)
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{
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semaphore_wait(&sfc_sema, TIMEOUT_BLOCK);
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}
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void SFC(void)
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{
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unsigned sr = REG_SFC_SR & ~REG_SFC_INTC;
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if(jz_vreadf(sr, SFC_SR, OVER)) {
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jz_overwritef(SFC_SCR, CLR_OVER(1));
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sfc_status = SFC_STATUS_OVERFLOW;
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} else if(jz_vreadf(sr, SFC_SR, UNDER)) {
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jz_overwritef(SFC_SCR, CLR_UNDER(1));
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sfc_status = SFC_STATUS_UNDERFLOW;
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} else if(jz_vreadf(sr, SFC_SR, END)) {
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jz_overwritef(SFC_SCR, CLR_END(1));
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sfc_status = SFC_STATUS_OK;
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} else {
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panicf("SFC IRQ bug");
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return;
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}
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/* Not sure this is wholly correct */
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if(sfc_status != SFC_STATUS_OK)
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jz_overwritef(SFC_TRIG, STOP(1));
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REG_SFC_INTC = 0x1f;
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semaphore_release(&sfc_sema);
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}
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#else
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/* Note the X1000 is *very* picky about how the SFC FIFOs are accessed
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* so please do NOT try to rearrange the code without testing it first!
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*/
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void sfc_fifo_read(unsigned* buffer, int data_bytes)
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{
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int data_words = (data_bytes + 3) / 4;
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while(data_words > 0) {
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if(jz_readf(SFC_SR, RREQ)) {
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jz_overwritef(SFC_SCR, CLR_RREQ(1));
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int amount = data_words > FIFO_THRESH ? FIFO_THRESH : data_words;
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data_words -= amount;
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while(amount > 0) {
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*buffer++ = REG_SFC_DATA;
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amount -= 1;
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}
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}
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}
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}
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void sfc_fifo_write(const unsigned* buffer, int data_bytes)
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{
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int data_words = (data_bytes + 3) / 4;
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while(data_words > 0) {
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if(jz_readf(SFC_SR, TREQ)) {
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jz_overwritef(SFC_SCR, CLR_TREQ(1));
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int amount = data_words > FIFO_THRESH ? FIFO_THRESH : data_words;
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data_words -= amount;
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while(amount > 0) {
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REG_SFC_DATA = *buffer++;
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amount -= 1;
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}
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}
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}
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}
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static void sfc_wait_end(void)
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{
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while(jz_readf(SFC_SR, END) == 0);
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jz_overwritef(SFC_SCR, CLR_TREQ(1));
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}
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#endif /* NEED_SFC_DMA */
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int sfc_exec(const sfc_op* op)
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{
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#ifdef NEED_SFC_DMA
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uint32_t intc_clear = jz_orm(SFC_INTC, MSK_END);
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#endif
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if(op->flags & (SFC_FLAG_READ|SFC_FLAG_WRITE)) {
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jz_writef(SFC_TRAN_CONF(0), DATA_EN(1));
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REG_SFC_TRAN_LENGTH = op->data_bytes;
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#ifdef NEED_SFC_DMA
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REG_SFC_MEM_ADDR = PHYSADDR(op->buffer);
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#endif
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if(op->flags & SFC_FLAG_READ)
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{
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jz_writef(SFC_GLB, TRAN_DIR_V(READ));
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#ifdef NEED_SFC_DMA
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discard_dcache_range(op->buffer, op->data_bytes);
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intc_clear |= jz_orm(SFC_INTC, MSK_OVER);
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#endif
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}
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else
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{
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jz_writef(SFC_GLB, TRAN_DIR_V(WRITE));
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#ifdef NEED_SFC_DMA
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commit_dcache_range(op->buffer, op->data_bytes);
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intc_clear |= jz_orm(SFC_INTC, MSK_UNDER);
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#endif
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}
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} else {
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jz_writef(SFC_TRAN_CONF(0), DATA_EN(0));
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REG_SFC_TRAN_LENGTH = 0;
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#ifdef NEED_SFC_DMA
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REG_SFC_MEM_ADDR = 0;
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#endif
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}
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bool dummy_first = (op->flags & SFC_FLAG_DUMMYFIRST) != 0;
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jz_writef(SFC_TRAN_CONF(0),
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MODE(op->mode), POLL_EN(0),
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ADDR_WIDTH(op->addr_bytes),
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PHASE_FMT(dummy_first ? 1 : 0),
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DUMMY_BITS(op->dummy_bits),
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COMMAND(op->command), CMD_EN(1));
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REG_SFC_DEV_ADDR(0) = op->addr_lo;
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REG_SFC_DEV_PLUS(0) = op->addr_hi;
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#ifdef NEED_SFC_DMA
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sfc_status = SFC_STATUS_PENDING;
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timeout_register(&sfc_lockup_tmo, sfc_lockup_tmo_cb, 10*HZ, 0);
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REG_SFC_SCR = 0x1f;
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REG_SFC_INTC &= ~intc_clear;
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#endif
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jz_overwritef(SFC_TRIG, FLUSH(1));
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jz_overwritef(SFC_TRIG, START(1));
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#ifndef NEED_SFC_DMA
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if(op->flags & SFC_FLAG_READ)
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sfc_fifo_read((unsigned*)op->buffer, op->data_bytes);
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if(op->flags & SFC_FLAG_WRITE)
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sfc_fifo_write((const unsigned*)op->buffer, op->data_bytes);
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#endif
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sfc_wait_end();
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#ifdef NEED_SFC_DMA
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if(op->flags & SFC_FLAG_READ)
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discard_dcache_range(op->buffer, op->data_bytes);
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#endif
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return sfc_status;
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}
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