355 lines
18 KiB
C
355 lines
18 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.8
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* XML versions: stmp3700:3.2.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3700__GPIOMON__H__
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#define __HEADERGEN__STMP3700__GPIOMON__H__
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#define REGS_GPIOMON_BASE (0x8003c300)
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#define REGS_GPIOMON_VERSION "3.2.0"
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/**
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* Register: HW_GPIOMON_BANK0_DATAIN
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* Address: 0
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* SCT: no
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*/
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#define HW_GPIOMON_BANK0_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x0))
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#define BP_GPIOMON_BANK0_DATAIN_DATA 0
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#define BM_GPIOMON_BANK0_DATAIN_DATA 0xffffffff
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#define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK1_DATAIN
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* Address: 0x10
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* SCT: no
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*/
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#define HW_GPIOMON_BANK1_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x10))
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#define BP_GPIOMON_BANK1_DATAIN_DATA 0
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#define BM_GPIOMON_BANK1_DATAIN_DATA 0xffffffff
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#define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK2_DATAIN
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* Address: 0x20
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* SCT: no
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*/
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#define HW_GPIOMON_BANK2_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x20))
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#define BP_GPIOMON_BANK2_DATAIN_DATA 0
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#define BM_GPIOMON_BANK2_DATAIN_DATA 0xffffffff
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#define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK3_DATAIN
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* Address: 0x30
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* SCT: no
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*/
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#define HW_GPIOMON_BANK3_DATAIN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x30))
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#define BP_GPIOMON_BANK3_DATAIN_DATA 0
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#define BM_GPIOMON_BANK3_DATAIN_DATA 0xffffffff
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#define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK0_DATAOUT
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* Address: 0x40
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK0_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x0))
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#define HW_GPIOMON_BANK0_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x4))
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#define HW_GPIOMON_BANK0_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0x8))
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#define HW_GPIOMON_BANK0_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x40 + 0xc))
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#define BP_GPIOMON_BANK0_DATAOUT_DATA 0
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#define BM_GPIOMON_BANK0_DATAOUT_DATA 0xffffffff
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#define BF_GPIOMON_BANK0_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK1_DATAOUT
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* Address: 0x50
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK1_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x0))
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#define HW_GPIOMON_BANK1_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x4))
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#define HW_GPIOMON_BANK1_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0x8))
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#define HW_GPIOMON_BANK1_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x50 + 0xc))
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#define BP_GPIOMON_BANK1_DATAOUT_DATA 0
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#define BM_GPIOMON_BANK1_DATAOUT_DATA 0xffffffff
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#define BF_GPIOMON_BANK1_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK2_DATAOUT
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* Address: 0x60
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK2_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x0))
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#define HW_GPIOMON_BANK2_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x4))
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#define HW_GPIOMON_BANK2_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0x8))
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#define HW_GPIOMON_BANK2_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x60 + 0xc))
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#define BP_GPIOMON_BANK2_DATAOUT_DATA 0
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#define BM_GPIOMON_BANK2_DATAOUT_DATA 0xffffffff
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#define BF_GPIOMON_BANK2_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK3_DATAOUT
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* Address: 0x70
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK3_DATAOUT (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x0))
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#define HW_GPIOMON_BANK3_DATAOUT_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x4))
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#define HW_GPIOMON_BANK3_DATAOUT_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0x8))
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#define HW_GPIOMON_BANK3_DATAOUT_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x70 + 0xc))
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#define BP_GPIOMON_BANK3_DATAOUT_DATA 0
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#define BM_GPIOMON_BANK3_DATAOUT_DATA 0xffffffff
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#define BF_GPIOMON_BANK3_DATAOUT_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK0_DATAOEN
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* Address: 0x80
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK0_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x0))
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#define HW_GPIOMON_BANK0_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x4))
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#define HW_GPIOMON_BANK0_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0x8))
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#define HW_GPIOMON_BANK0_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x80 + 0xc))
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#define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0
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#define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0xffffffff
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#define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK1_DATAOEN
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* Address: 0x90
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK1_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x0))
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#define HW_GPIOMON_BANK1_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x4))
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#define HW_GPIOMON_BANK1_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0x8))
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#define HW_GPIOMON_BANK1_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x90 + 0xc))
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#define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0
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#define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0xffffffff
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#define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK2_DATAOEN
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* Address: 0xa0
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK2_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x0))
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#define HW_GPIOMON_BANK2_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x4))
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#define HW_GPIOMON_BANK2_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0x8))
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#define HW_GPIOMON_BANK2_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xa0 + 0xc))
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#define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0
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#define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0xffffffff
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#define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_BANK3_DATAOEN
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* Address: 0xb0
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* SCT: yes
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*/
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#define HW_GPIOMON_BANK3_DATAOEN (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x0))
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#define HW_GPIOMON_BANK3_DATAOEN_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x4))
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#define HW_GPIOMON_BANK3_DATAOEN_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0x8))
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#define HW_GPIOMON_BANK3_DATAOEN_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xb0 + 0xc))
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#define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0
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#define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0xffffffff
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#define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_CTRL
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* Address: 0xc0
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* SCT: yes
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*/
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#define HW_GPIOMON_CTRL (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x0))
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#define HW_GPIOMON_CTRL_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x4))
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#define HW_GPIOMON_CTRL_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0x8))
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#define HW_GPIOMON_CTRL_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xc0 + 0xc))
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#define BP_GPIOMON_CTRL_RSRVD 4
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#define BM_GPIOMON_CTRL_RSRVD 0xfffffff0
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#define BF_GPIOMON_CTRL_RSRVD(v) (((v) << 4) & 0xfffffff0)
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#define BP_GPIOMON_CTRL_PINMUX_ALT_RESET 3
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#define BM_GPIOMON_CTRL_PINMUX_ALT_RESET 0x8
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#define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) << 3) & 0x8)
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#define BP_GPIOMON_CTRL_OEN_8MA 2
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#define BM_GPIOMON_CTRL_OEN_8MA 0x4
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#define BF_GPIOMON_CTRL_OEN_8MA(v) (((v) << 2) & 0x4)
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#define BP_GPIOMON_CTRL_OEN_4MA 1
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#define BM_GPIOMON_CTRL_OEN_4MA 0x2
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#define BF_GPIOMON_CTRL_OEN_4MA(v) (((v) << 1) & 0x2)
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#define BP_GPIOMON_CTRL_OEN_NAND 0
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#define BM_GPIOMON_CTRL_OEN_NAND 0x1
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#define BF_GPIOMON_CTRL_OEN_NAND(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_GPIOMON_ALT1_PINMUX_BANK0
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* Address: 0xd0
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT1_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x0))
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#define HW_GPIOMON_ALT1_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x4))
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#define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0x8))
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#define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xd0 + 0xc))
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#define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0
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#define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0xffffffff
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#define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT1_PINMUX_BANK1
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* Address: 0xe0
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT1_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x0))
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#define HW_GPIOMON_ALT1_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x4))
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#define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0x8))
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#define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xe0 + 0xc))
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#define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0
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#define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0xffffffff
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#define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT1_PINMUX_BANK2
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* Address: 0xf0
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT1_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x0))
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#define HW_GPIOMON_ALT1_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x4))
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#define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0x8))
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#define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0xf0 + 0xc))
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#define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0
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#define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0xffffffff
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#define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT1_PINMUX_BANK3
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* Address: 0x100
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT1_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x0))
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#define HW_GPIOMON_ALT1_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x4))
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#define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0x8))
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#define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x100 + 0xc))
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#define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0
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#define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0xffffffff
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#define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT2_PINMUX_BANK0
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* Address: 0x110
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT2_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x0))
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#define HW_GPIOMON_ALT2_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x4))
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#define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0x8))
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#define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x110 + 0xc))
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#define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0
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#define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0xffffffff
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#define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT2_PINMUX_BANK1
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* Address: 0x120
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT2_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x0))
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#define HW_GPIOMON_ALT2_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x4))
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#define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0x8))
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#define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x120 + 0xc))
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#define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0
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#define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0xffffffff
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#define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT2_PINMUX_BANK2
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* Address: 0x130
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT2_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x0))
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#define HW_GPIOMON_ALT2_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x4))
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#define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0x8))
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#define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x130 + 0xc))
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#define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0
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#define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0xffffffff
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#define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT2_PINMUX_BANK3
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* Address: 0x140
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT2_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x0))
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#define HW_GPIOMON_ALT2_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x4))
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#define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0x8))
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#define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x140 + 0xc))
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#define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0
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#define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0xffffffff
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#define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT3_PINMUX_BANK0
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* Address: 0x150
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT3_PINMUX_BANK0 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x0))
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#define HW_GPIOMON_ALT3_PINMUX_BANK0_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x4))
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#define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0x8))
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#define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x150 + 0xc))
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#define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0
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#define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0xffffffff
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#define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT3_PINMUX_BANK1
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* Address: 0x160
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT3_PINMUX_BANK1 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x0))
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#define HW_GPIOMON_ALT3_PINMUX_BANK1_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x4))
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#define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0x8))
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#define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x160 + 0xc))
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#define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0
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#define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0xffffffff
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#define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT3_PINMUX_BANK2
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* Address: 0x170
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT3_PINMUX_BANK2 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x0))
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#define HW_GPIOMON_ALT3_PINMUX_BANK2_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x4))
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#define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0x8))
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#define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x170 + 0xc))
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#define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0
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#define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0xffffffff
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#define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPIOMON_ALT3_PINMUX_BANK3
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* Address: 0x180
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* SCT: yes
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*/
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#define HW_GPIOMON_ALT3_PINMUX_BANK3 (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x0))
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#define HW_GPIOMON_ALT3_PINMUX_BANK3_SET (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x4))
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#define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0x8))
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#define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG (*(volatile unsigned long *)(REGS_GPIOMON_BASE + 0x180 + 0xc))
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#define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0
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#define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0xffffffff
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#define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) (((v) << 0) & 0xffffffff)
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#endif /* __HEADERGEN__STMP3700__GPIOMON__H__ */
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