2f16d4f1b3
Changes made: Combine bootloader/h10.c and bootloader/e200.c into a common bootloader file (bootloader/main-pp.c) to be used by all mi4 based PortalPlayer targets. The file bootloader/main-pp.c is based off the old bootloader/h10.c with some minor changes to allow it to work on the Sansa too. This effectively adds a Sansa bootloader. Define MODEL_NAME string in config-*.h for use in bootloader. Split crt0-pp.S into separate files for bootloader and normal builds. Bootloader code is now in crt0-pp-bl.S while normal build code stays in crt0-pp.S. Improvements to crt0-pp.S and crt0-pp-bl.S (mostly to make it more multiprocessor safe): * Leave space in bootloader at 0xe0-0xeb since scramble writes over there when it creates the mi4 file (don't leave space for iPods since it's not needed and all code in crt0-pp-bl.S needs to fit before the boot_table at 0x100). * Remove unused DEBUG and STUB code from crt0-pp.S. * Make CPU wait for COP to be sleeping when we put the COP to sleep. * Invalidate COP cache when COP wakes * Flush CPU cache before waking COP * Make sure only the CPU clears the BSS (not the COP) * Make sure only the CPU sets up its own stack (not the COP) Rolo works on H10, so enable it. Make Sansa e200 use rockbox.e200 rather than PP5022.mi4 for 'Normal' builds. This makes updating rockbox simpler as we don't need to go through the firmware update procedure, but rather just put a new rockbox.e200 on the device. rockbox.e200 uses a simple 'add' checksum. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11815 a1c6a512-1295-4272-9138-f99709370657
312 lines
7.6 KiB
ArmAsm
312 lines
7.6 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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.global start
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start:
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/* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
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* loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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*/
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#if CONFIG_CPU == PP5002
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.equ PROC_ID, 0xc4000000
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.equ COP_CTRL, 0xcf004058
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.equ COP_STATUS, 0xcf004050
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.equ IIS_CONFIG, 0xc0002500
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.equ SLEEP, 0xca
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.equ WAKE, 0xce
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.equ SLEEPING, 0x4000
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#else
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.equ PROC_ID, 0x60000000
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.equ COP_CTRL, 0x60007004
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.equ COP_STATUS, 0x60007004
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.equ IIS_CONFIG, 0x70002800
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.equ SLEEP, 0x80000000
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.equ WAKE, 0x0
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.equ SLEEPING, 0x80000000
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.equ CACHE_CTRL, 0x6000c000
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
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b pad_skip
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.space 50*4 /* (more than enough) space for exception vectors */
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pad_skip:
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#ifdef SANSA_E200
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/* On the Sansa, copying the vectors fails if the cache is initialised */
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ldr r1, =CACHE_CTRL
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mov r2, #0x0
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str r2, [r1]
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#endif
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/* We need to remap memory from wherever SDRAM is mapped natively, to
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base address 0, so we can put our exception vectors there. We don't
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want to do this remapping while executing from SDRAM, so we copy the
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remapping code to IRAM, then execute from there. Hence, the following
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code is compiled for address 0, but is currently executing at either
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0x28000000 or 0x10000000, depending on chipset version. Do not use any
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absolute addresses until remapping has been done. */
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ldr r1, =0x40000000
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ldr r2, =remap_start
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ldr r3, =remap_end
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and r5, pc, #0xff000000 /* adjust for execute address */
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orr r2, r2, r5
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orr r3, r3, r5
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/* copy the code to 0x40000000 */
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1:
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ldr r4, [r2], #4
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str r4, [r1], #4
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cmp r2, r3
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ble 1b
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ldr r3, =0x3f84 /* r3 and r1 values here are magic, don't touch */
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orr r3, r3, r5 /* adjust for execute address */
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ldr r2, =0xf000f014
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mov r1, #0x3a00
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ldr r0, =0xf000f010
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mov pc, #0x40000000
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remap_start:
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str r1, [r0]
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str r3, [r2]
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ldr r0, L_post_remap
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mov pc, r0
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L_post_remap: .word remap_end
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remap_end:
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/* After doing the remapping, send the COP to sleep.
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On wakeup it will go to cop_init */
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/* Find out which processor we are */
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ldr r0, =PROC_ID
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ldr r0, [r0]
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and r0, r0, #0xff
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cmp r0, #0x55
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beq cpu_init
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/* put us (co-processor) to sleep */
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ldr r4, =COP_CTRL
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mov r3, #SLEEP
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str r3, [r4]
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ldr pc, =cop_init
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cpu_init:
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/* Wait for COP to be sleeping */
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ldr r4, =COP_STATUS
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1:
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ldr r3, [r4]
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ands r3, r3, #SLEEPING
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beq 1b
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =fiq_stack
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/* We'll load the banked FIQ mode registers with useful values here.
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These values will be used in the FIQ handler in pcm_playback.c */
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ldr r12, =IIS_CONFIG
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ldr r11, =p
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/* Let abort and undefined modes use IRQ stack */
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msr cpsr_c, #0xd7
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb
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ldr sp, =irq_stack
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/* Switch to supervisor mode */
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msr cpsr_c, #0xd3
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ldr sp, =stackend
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bl main
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/* main() should never return */
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cop_init:
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#if CONFIG_CPU != PP5002
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/* COP: Invalidate cache */
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ldr r0, =0xf000f044
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ldr r1, [r0]
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orr r1, r1, #0x6
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str r1, [r0]
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ldr r0, =0x6000c000
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1:
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ldr r1, [r0]
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tst r1, #0x8000
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bne 1b
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#endif
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/* Setup stack for COP */
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ldr sp, =cop_stackend
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mov r3, sp
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ldr r2, =cop_stackbegin
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ldr r4, =0xdeadbeef
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2:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 2b
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ldr sp, =cop_stackend
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/* Run cop_main() in apps/main.c */
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bl cop_main
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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/* Exception vectors */
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.global vectors
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vectors:
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.word start
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.word undef_instr_handler
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.word software_int_handler
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.word prefetch_abort_handler
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.word data_abort_handler
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.word reserved_handler
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.word irq_handler
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.word fiq_handler
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.text
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#ifndef STUB
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.global irq
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.global fiq
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.global UIE
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#endif
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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we're in. Second parameter is exception number, used for a string lookup
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in UIE.
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*/
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undef_instr_handler:
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mov r0, lr
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mov r1, #0
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b UIE
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/* We run supervisor mode most of the time, and should never see a software
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exception being thrown. Perhaps make it illegal and call UIE?
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*/
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software_int_handler:
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reserved_handler:
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movs pc, lr
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prefetch_abort_handler:
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sub r0, lr, #4
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mov r1, #1
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b UIE
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fiq_handler:
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@ Branch straight to FIQ handler in pcm_playback.c. This also handles the
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@ the correct return sequence.
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ldr pc, =fiq
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data_abort_handler:
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sub r0, lr, #8
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mov r1, #2
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b UIE
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irq_handler:
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#ifndef STUB
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stmfd sp!, {r0-r3, r12, lr}
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bl irq
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ldmfd sp!, {r0-r3, r12, lr}
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#endif
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subs pc, lr, #4
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#ifdef STUB
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UIE:
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b UIE
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#endif
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/* 256 words of IRQ stack */
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.space 256*4
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irq_stack:
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/* 256 words of FIQ stack */
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.space 256*4
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fiq_stack:
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