300 lines
9.1 KiB
C
300 lines
9.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 Marcin Bukat
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* Copyright (C) 2011 Andrew Ryabinin
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "audio.h"
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#include "string.h"
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#include "panic.h"
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#include "audiohw.h"
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#include "sound.h"
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#include "pcm-internal.h"
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static int locked = 0;
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/* Mask the DMA interrupt */
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void pcm_play_lock(void)
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{
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if (++locked == 1)
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{
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int old = disable_irq_save();
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INTC_IMR &= ~IRQ_ARM_HDMA; /* mask HDMA interrupt */
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restore_irq(old);
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}
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}
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/* Unmask the DMA interrupt if enabled */
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void pcm_play_unlock(void)
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{
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if(--locked == 0)
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{
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int old = disable_irq_save();
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INTC_IMR |= IRQ_ARM_HDMA; /* unmask HDMA interrupt */
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restore_irq(old);
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}
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}
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void pcm_play_dma_stop(void)
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{
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HDMA_CON0 = 0x00;
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HDMA_ISR = 0x00;
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locked = 1;
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}
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static void hdma_i2s_transfer(const void *addr, size_t size)
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{
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SCU_CLKCFG &= ~CLKCFG_HDMA; /* enable HDMA clock */
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commit_discard_dcache_range(addr, size);
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HDMA_ISRC0 = (uint32_t)addr; /* source address */
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HDMA_IDST0 = (uint32_t)&I2S_TXR; /* i2s tx fifo */
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HDMA_ICNT0 = (uint16_t)((size>>2) - 1); /* number of dma transactions
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* of transfer size bytes
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* (zero based)
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*/
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HDMA_ISR = ((1<<13) | /* mask ch1 accumulation overflow irq */
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(1<<12) | /* mask ch0 accumulation overflow irq */
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(1<<11) | /* mask ch1 page count down irq */
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(0<<10) | /* UNMASK ch0 page count down irq */
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(1<<9) | /* mask ch0 transfer irq */
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(1<<8) | /* mask ch1 transfer irq */
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(0<<5) | /* clear ch1 accumulation overflow flag */
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(0<<4) | /* clear ch0 accumulation overflow flag */
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(0<<3) | /* clear ch1 count down to zero flag */
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(0<<2) | /* clear ch0 count down to zero flag */
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(0<<1) | /* clear ch1 active flag */
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(0<<0)); /* clear ch0 active flag */
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HDMA_ISCNT0 = 0x07; /* slice size in transfer size units (zero base) */
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HDMA_IPNCNTD0 = 0x01; /* page count */
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HDMA_CON0 = ((0<<23) | /* page mode */
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(1<<22) | /* slice mode */
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(1<<21) | /* DMA enable */
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(1<<18) | /* generate interrupt */
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(0<<16) | /* on-the-fly is not supported by rk27xx */
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(5<<13) | /* transfer mode inc8 */
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(6<<9) | /* external hdreq from i2s tx */
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(0<<7) | /* increment source address */
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(1<<5) | /* fixed destination address */
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(2<<3) | /* transfer size = 32bits word */
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(0<<1) | /* command of software DMA (not relevant) */
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(1<<0)); /* hardware trigger DMA mode */
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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/* Stop any DMA in progress */
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pcm_play_dma_stop();
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/* kick in DMA transfer */
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hdma_i2s_transfer(addr, size);
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}
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/* pause DMA transfer by disabling clock to DMA module */
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void pcm_play_dma_pause(bool pause)
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{
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if(pause)
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{
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SCU_CLKCFG |= CLKCFG_HDMA;
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locked = 1;
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}
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else
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{
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SCU_CLKCFG &= ~CLKCFG_HDMA;
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locked = 0;
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}
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}
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static void i2s_init(void)
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{
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#if defined(HAVE_RK27XX_CODEC)
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/* iomux I2S internal */
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SCU_IOMUXA_CON &= ~(1<<19); /* i2s external bit */
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SCU_IOMUXB_CON &= ~((1<<4) | /* i2s_mclk */
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(1<<3) | /* i2s_sdo */
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(1<<2) | /* i2s_sdi */
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(1<<1) | /* i2s_lrck */
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(1<<0)); /* i2s_bck */
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#else
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/* iomux I2S external */
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SCU_IOMUXA_CON |= (1<<19); /* i2s external bit */
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SCU_IOMUXB_CON |= ((1<<4) | /* i2s_mclk */
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(1<<3) | /* i2s_sdo */
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(1<<2) | /* i2s_sdi */
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(1<<1) | /* i2s_lrck */
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(1<<0)); /* i2s_bck */
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#endif
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/* enable i2s clocks */
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SCU_CLKCFG &= ~(CLKCFG_PCLK_I2S | CLKCFG_I2S);
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/* configure I2S module */
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I2S_IER = 0; /* disable all i2s interrupts */
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I2S_TXCTL = (1<<16) | /* LRCK/SCLK = 64 */
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(4<<8) | /* MCLK/SCLK = 4 */
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(1<<4) | /* 16bit samples */
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(0<<3) | /* stereo */
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(0<<1) | /* I2S IF */
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#ifdef CODEC_SLAVE
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(1<<0); /* master mode */
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#else
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(0<<0); /* slave mode */
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#endif
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/* the fifo is 16x32bits according to my tests
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* while the docs state 32x32bits
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*/
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I2S_FIFOSTS = (1<<18) | /* Tx trigger level half full */
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(1<<16); /* Rx trigger level half full */
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I2S_OPR = (1<<17) | /* reset Tx */
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(1<<16) | /* reset Rx */
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(0<<6) | /* HDMA Req1 enable */
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(1<<5) | /* HDMA Req2 disable */
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(0<<4) | /* Req1 for Tx fifo */
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(1<<3) | /* Req2 for Rx fifo */
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(0<<2) | /* normal operation */
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#ifdef CODEC_SLAVE
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(1<<1) | /* start Tx (master mode) */
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(0<<0); /* do not start Rx (master mode) */
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/* setting Rx bit to 1 result in choppy audio */
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#else
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(0<<1) | /* not used in slave mode */
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(0<<0); /* not used in slave mode */
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#endif
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}
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#ifdef CODEC_SLAVE
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/* When codec is slave we need to setup i2s MCLK clock using codec pll.
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* The MCLK frequency is 256*codec frequency as i2s setup is:
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* LRCK/SCLK = 64 and MCLK/SCLK = 4 (see i2s_init() for reference)
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*
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* PLL output frequency:
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* Fout = ((Fref / (CLKR+1)) * (CLKF+1)) / (CLKOD+1)
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* Fref = 24 MHz
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*/
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static void set_codec_freq(unsigned int freq)
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{
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long timeout;
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/* {CLKR, CLKF, CLKOD, CODECPLL_DIV} */
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static const unsigned int pcm_freq_params[HW_NUM_FREQ][4] =
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{
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[HW_FREQ_96] = {24, 255, 4, 1},
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[HW_FREQ_48] = {24, 127, 4, 1},
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[HW_FREQ_44] = {24, 293, 4, 4},
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[HW_FREQ_32] = {24, 127, 4, 2},
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[HW_FREQ_24] = {24, 127, 4, 3},
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[HW_FREQ_22] = {24, 146, 4, 4},
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[HW_FREQ_16] = {24, 127, 5, 4},
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[HW_FREQ_12] = {24, 127, 4, 7},
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[HW_FREQ_11] = {24, 146, 4, 9},
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[HW_FREQ_8] = {24, 127, 5, 9},
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};
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/* select divider output from codec pll */
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SCU_DIVCON1 &= ~((1<<9) | (0xF<<5));
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SCU_DIVCON1 |= (pcm_freq_params[freq][3]<<5);
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/* Codec PLL power up */
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SCU_PLLCON3 &= ~(1<<22);
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SCU_PLLCON3 = (1<<24) | /* Saturation behavior enable */
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(1<<23) | /* Enable fast locking circuit */
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(pcm_freq_params[freq][0]<<16) | /* CLKR factor */
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(pcm_freq_params[freq][1]<<4) | /* CLKF factor */
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(pcm_freq_params[freq][2]<<1) ; /* CLKOD factor */
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/* wait for CODEC PLL lock with 10 ms timeout
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* datasheet states that pll lock should take approx. 0.3 ms
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*/
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timeout = current_tick + (HZ/100);
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while (!(SCU_STATUS & (1<<2)))
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if (TIME_AFTER(current_tick, timeout))
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break;
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}
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#endif
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void pcm_play_dma_init(void)
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{
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/* unmask HDMA interrupt in INTC */
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INTC_IMR |= IRQ_ARM_HDMA;
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INTC_IECR |= IRQ_ARM_HDMA;
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audiohw_preinit();
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i2s_init();
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}
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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}
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void pcm_dma_apply_settings(void)
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{
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#ifdef CODEC_SLAVE
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set_codec_freq(pcm_fsel);
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#endif
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audiohw_set_frequency(pcm_fsel);
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}
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size_t pcm_get_bytes_waiting(void)
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{
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/* current terminate count is in transfer size units (4bytes here) */
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return (HDMA_CCNT0 & 0xffff)<<2;
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}
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/* audio DMA ISR called when chunk from callers buffer has been transfered */
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void INT_HDMA(void)
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{
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const void *start;
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size_t size;
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if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &start, &size))
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{
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hdma_i2s_transfer(start, size);
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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uint32_t addr;
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int old = disable_irq_save();
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addr = HDMA_CSRC0;
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*count = ((HDMA_CCNT0 & 0xffff)<<2);
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restore_interrupt(old);
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return (void*)addr;
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}
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/****************************************************************************
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** Recording DMA transfer
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**/
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/* TODO */
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