ffefe0c08b
Note : SH has TIMER_FREQ defined to CPU_FREQ, so any code wanting it must include #config.h before #cpu.h git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21560 a1c6a512-1295-4272-9138-f99709370657
255 lines
11 KiB
C
255 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2004 by Thom Johansen
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __PP5002_H__
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#define __PP5002_H__
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/* Much info gleaned and/or copied from the iPodLinux project. */
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#define DRAM_START 0x28000000
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/* LCD bridge */
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#define LCD1_BASE 0xc0001000
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#define LCD1_CONTROL (*(volatile unsigned long *)(0xc0001000))
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#define LCD1_CMD (*(volatile unsigned long *)(0xc0001008))
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#define LCD1_DATA (*(volatile unsigned long *)(0xc0001010))
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#define LCD1_BUSY_MASK 0x8000
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/* I2S controller */
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/* FIFO slot bits 7-0 are not implemented and so use of packed samples
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* appears to be impossible. */
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#define IISCONFIG (*(volatile unsigned long *)(0xc0002500))
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#define IISFIFO_CFG (*(volatile unsigned long *)(0xc000251c))
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#define IISFIFO_WR (*(volatile unsigned long *)(0xc0002540))
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#define IISFIFO_RD (*(volatile unsigned long *)(0xc0002580))
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/**
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* IISCONFIG bits:
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* | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
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* | | | | | | | | |
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* | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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* | | | | | | | | |
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* | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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* | | | | | | | | |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* | rw | rw | rw | MS | rw |TXFENB# | rw | ENB |
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*
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* # No effect observed on iPod 3g
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*/
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#define IIS_ENABLE (1 << 0)
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#define IIS_TXFIFOEN (1 << 2)
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#define IIS_MASTER (1 << 4)
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/**
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* IISFIFO_CFG bits:
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* | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
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* | | RXFull[3:0]$ | TXFree[3:1] >
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* | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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* >TXFre[0]| | | | | | RXCLR | TXCLR |
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* | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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* | rw | rw | rw | rw | rw | rw | IRQTX | rw |
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* | 7* | 6* | 5* | 4* | 3 | 2 | 1 | 0 |
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* |RXEMPTY | RXSAFE | RXDNGR | RXFULL | TXFULL | TXSAFE | TXDNGR |TXEMPTY |
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*
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* $Could be RXFree
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* *Meaning isn't certain yet.
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* More concerted recording work will reveal.
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*/
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#define IIS_IRQTX_REG IISFIFO_CFG
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#define IIS_IRQRX_REG IISFIFO_CFG
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#define IIS_RX_FULL_MASK (0xf << 27)
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#define IIS_RX_FULL_COUNT ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 27)
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#define IIS_TX_FREE_MASK (0xf << 23) /* 0xf = 16 or 15 free */
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#define IIS_TX_FREE_COUNT ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 23)
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#define IIS_TX_IS_EMPTY ((IISFIFO_CFG & IIS_TXEMPTY) != 0)
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#define IIS_RXCLR (1 << 17) /* Resets *could* be reversed */
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#define IIS_TXCLR (1 << 16)
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#define IIS_IRQTX (1 << 9)
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#define IIS_TXFULL (1 << 3) /* All slots occupied */
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#define IIS_TXSAFE (1 << 2) /* FIFO >= 3/4 full */
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#define IIS_TXDANGER (1 << 1) /* FIFO <= 1/4 full */
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#define IIS_TXEMPTY (1 << 0) /* No samples in FIFO */
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#define IIS_RXEMPTY (1 << 4) /* FIFO is empty */
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#define IDE_BASE 0xc0003000
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#define IDE_CFG_STATUS (*(volatile unsigned long *)(0xc0003024))
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#define USB_BASE 0xc0005000
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#define I2C_BASE 0xc0008000
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/* Processor ID */
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#define PROCESSOR_ID (*(volatile unsigned long *)(0xc4000000))
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#define PROC_ID_CPU 0x55
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#define PROC_ID_COP 0xaa
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#define GPIOA_ENABLE (*(volatile unsigned char *)(0xcf000000))
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#define GPIOB_ENABLE (*(volatile unsigned char *)(0xcf000004))
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#define GPIOC_ENABLE (*(volatile unsigned char *)(0xcf000008))
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#define GPIOD_ENABLE (*(volatile unsigned char *)(0xcf00000c))
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#define GPIOA_OUTPUT_EN (*(volatile unsigned char *)(0xcf000010))
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#define GPIOB_OUTPUT_EN (*(volatile unsigned char *)(0xcf000014))
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#define GPIOC_OUTPUT_EN (*(volatile unsigned char *)(0xcf000018))
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#define GPIOD_OUTPUT_EN (*(volatile unsigned char *)(0xcf00001c))
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#define GPIOA_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000020))
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#define GPIOB_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000024))
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#define GPIOC_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000028))
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#define GPIOD_OUTPUT_VAL (*(volatile unsigned char *)(0xcf00002c))
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#define GPIOA_INPUT_VAL (*(volatile unsigned char *)(0xcf000030))
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#define GPIOB_INPUT_VAL (*(volatile unsigned char *)(0xcf000034))
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#define GPIOC_INPUT_VAL (*(volatile unsigned char *)(0xcf000038))
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#define GPIOD_INPUT_VAL (*(volatile unsigned char *)(0xcf00003c))
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#define GPIOA_INT_STAT (*(volatile unsigned char *)(0xcf000040))
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#define GPIOB_INT_STAT (*(volatile unsigned char *)(0xcf000044))
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#define GPIOC_INT_STAT (*(volatile unsigned char *)(0xcf000048))
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#define GPIOD_INT_STAT (*(volatile unsigned char *)(0xcf00004c))
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#define GPIOA_INT_EN (*(volatile unsigned char *)(0xcf000050))
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#define GPIOB_INT_EN (*(volatile unsigned char *)(0xcf000054))
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#define GPIOC_INT_EN (*(volatile unsigned char *)(0xcf000058))
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#define GPIOD_INT_EN (*(volatile unsigned char *)(0xcf00005c))
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#define GPIOA_INT_LEV (*(volatile unsigned char *)(0xcf000060))
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#define GPIOB_INT_LEV (*(volatile unsigned char *)(0xcf000064))
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#define GPIOC_INT_LEV (*(volatile unsigned char *)(0xcf000068))
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#define GPIOD_INT_LEV (*(volatile unsigned char *)(0xcf00006c))
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#define GPIOA_INT_CLR (*(volatile unsigned char *)(0xcf000070))
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#define GPIOB_INT_CLR (*(volatile unsigned char *)(0xcf000074))
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#define GPIOC_INT_CLR (*(volatile unsigned char *)(0xcf000078))
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#define GPIOD_INT_CLR (*(volatile unsigned char *)(0xcf00007c))
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#define CPU_INT_STAT (*(volatile unsigned long *)(0xcf001000))
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#define COP_INT_STAT (*(volatile unsigned long *)(0xcf001004))
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#define CPU_FIQ_STAT (*(volatile unsigned long *)(0xcf001008))
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#define COP_FIQ_STAT (*(volatile unsigned long *)(0xcf00100c))
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#define INT_STAT (*(volatile unsigned long *)(0xcf001010))
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#define INT_FORCED_STAT (*(volatile unsigned long *)(0xcf001014))
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#define INT_FORCED_SET (*(volatile unsigned long *)(0xcf001018))
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#define INT_FORCED_CLR (*(volatile unsigned long *)(0xcf00101c))
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#define CPU_INT_EN_STAT (*(volatile unsigned long *)(0xcf001020))
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#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024))
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#define CPU_INT_DIS (*(volatile unsigned long *)(0xcf001028))
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#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
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#define COP_INT_EN_STAT (*(volatile unsigned long *)(0xcf001030))
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#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034))
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#define COP_INT_DIS (*(volatile unsigned long *)(0xcf001038))
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#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
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#define IDE_IRQ 1
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#define SER0_IRQ 4
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#define I2S_IRQ 5
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#define SER1_IRQ 7
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#define TIMER1_IRQ 11
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#define TIMER2_IRQ 12
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#define GPIO_IRQ 14
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#define DMA_OUT_IRQ 30
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#define DMA_IN_IRQ 31
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#define IDE_MASK (1 << IDE_IRQ)
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#define SER0_MASK (1 << SER0_IRQ)
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#define I2S_MASK (1 << I2S_IRQ)
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#define SER1_MASK (1 << SER1_IRQ)
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#define TIMER1_MASK (1 << TIMER1_IRQ)
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#define TIMER2_MASK (1 << TIMER2_IRQ)
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#define GPIO_MASK (1 << GPIO_IRQ)
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#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
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#define DMA_IN_MASK (1 << DMA_IN_IRQ)
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/* Yes, there is I2S_MASK but this cleans up the pcm code */
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#define IIS_MASK DMA_OUT_MASK
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#define TIMER1_CFG (*(volatile unsigned long *)(0xcf001100))
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#define TIMER1_VAL (*(volatile unsigned long *)(0xcf001104))
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#define TIMER2_CFG (*(volatile unsigned long *)(0xcf001108))
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#define TIMER2_VAL (*(volatile unsigned long *)(0xcf00110c))
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#define USEC_TIMER (*(volatile unsigned long *)(0xcf001110))
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#define TIMING1_CTL (*(volatile unsigned long *)(0xcf004000))
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#define TIMING2_CTL (*(volatile unsigned long *)(0xcf004008))
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#define PP_VER1 (*(volatile unsigned long *)(0xcf004030))
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#define PP_VER2 (*(volatile unsigned long *)(0xcf004034))
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#define PP_VER3 (*(volatile unsigned long *)(0xcf004038))
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#define PP_VER4 (*(volatile unsigned long *)(0xcf00403c))
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/* Processors Control */
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#define PROC_STAT (*(volatile unsigned long *)(0xcf004050))
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#define CPU_CTL (*(volatile unsigned char *)(0xcf004054))
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#define COP_CTL (*(volatile unsigned char *)(0xcf004058))
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#define CPU_SLEEPING 0x8000
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#define COP_SLEEPING 0x4000
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#define PROC_SLEEPING(core) (0x8000 >> (core))
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#define PROC_CTL(core) ((&CPU_CTL)[(core)*4])
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#define PROC_SLEEP 0xca
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#define PROC_WAKE 0xce
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/* Cache Control */
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#define CACHE_CTL (*(volatile unsigned long *)(0xcf004024))
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#define CACHE_RUN 0x1
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#define CACHE_INIT 0x2
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#define CACHE_MASK (*(volatile unsigned long *)(0xf000f020))
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#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f024))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long *)(0xf000c000))
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#define CACHE_INVALIDATE_BASE (*(volatile unsigned long *)(0xf0004000))
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#define CACHE_SIZE 0x2000 /* PP5002 has 8KB cache */
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#define CACHE_OP_UNKNOWN1 (1<<11) /* 0x800 */
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#define DEV_EN (*(volatile unsigned long *)(0xcf005000))
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#define DEV_RS (*(volatile unsigned long *)(0xcf005030))
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#define DEV_I2C (1<<8)
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#define DEV_I2S (1<<7)
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#define DEV_USB 0x400000
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#define CLOCK_ENABLE (*(volatile unsigned long *)(0xcf005008))
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#define CLOCK_SOURCE (*(volatile unsigned long *)(0xcf00500c))
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#define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010))
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#define PLL_DIV (*(volatile unsigned long *)(0xcf005018))
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#define PLL_MULT (*(volatile unsigned long *)(0xcf00501c))
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#define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038))
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#define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long *)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long *)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long *)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long *)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long *)(0xf000f01c))
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/* Timer frequency */
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/* Portalplayer chips use a microsecond timer. */
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#define TIMER_FREQ 1000000
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#endif
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