dd5dd8cfd9
The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
419 lines
15 KiB
ArmAsm
419 lines
15 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */
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#if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260
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/* MMU present but unused */
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#define HAVE_TEST_AND_CLEAN_CACHE
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#elif CONFIG_CPU == DM320 || CONFIG_CPU == AS3525v2
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#define USE_MMU
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#define HAVE_TEST_AND_CLEAN_CACHE
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#elif CONFIG_CPU == AS3525
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#define USE_MMU
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#define CACHE_SIZE 8
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#elif CONFIG_CPU == S3C2440
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#define USE_MMU
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#define CACHE_SIZE 16
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#elif CONFIG_CPU == S5L8700 || CONFIG_CPU == S5L8701
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/* MMU not present */
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#define CACHE_SIZE 4
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#else
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#error Cache settings unknown for this CPU !
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#endif /* CPU specific configuration */
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@ Index format: 31:26 = index, N:5 = segment, remainder = SBZ
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@ assume 64-way set associative separate I/D caches
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@ CACHE_SIZE = N (kB) = N*2^10 B
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@ number of lines = N*2^(10-CACHEALIGN_BITS)
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@ Index bits = 6
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@ Segment loops = N*2^(10-CACHEALIGN_BITS-6) = N*2^(4-CACHEALIGN_BITS)
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@ Segment loops = N/2^(CACHEALIGN_BITS - 4)
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@ Segment loops = N/(1<<(CACHEALIGN_BITS - 4))
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#ifdef CACHE_SIZE
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#if CACHEALIGN_BITS == 4
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#define INDEX_STEPS CACHE_SIZE
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#elif CACHEALIGN_BITS == 5
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#define INDEX_STEPS (CACHE_SIZE/2)
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#endif /* CACHEALIGN_BITS */
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@ assume 64-way set associative separate I/D caches (log2(64) == 6)
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@ Index format: 31:26 = index, M:N = segment, remainder = SBZ
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@ Segment bits = log2(cache size in bytes / cache line size in byte) - Index bits (== 6)
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@ N = CACHEALIGN_BITS
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#endif /* CACHE_SIZE */
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#ifdef USE_MMU
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/** MMU setup **/
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/*
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* void ttb_init(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global ttb_init
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.type ttb_init, %function
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ttb_init:
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ldr r0, =TTB_BASE_ADDR @
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mvn r1, #0 @
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mcr p15, 0, r0, c2, c0, 0 @ Set the TTB base address
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mcr p15, 0, r1, c3, c0, 0 @ Set all domains to manager status
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bx lr @
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.size ttb_init, .-ttb_init
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/*
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* void map_section(unsigned int pa, unsigned int va, int mb, int flags);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global map_section
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.type map_section, %function
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map_section:
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@ align to 1MB
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@ pa &= (-1 << 20);
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mov r0, r0, lsr #20
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mov r0, r0, lsl #20
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@ pa |= (flags | 0x412);
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@ bit breakdown:
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@ 10: superuser - r/w, user - no access
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@ 4: should be "1"
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@ 3,2: Cache flags (flags (r3))
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@ 1: Section signature
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orr r0, r0, r3
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orr r0, r0, #0x410
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orr r0, r0, #0x2
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@ unsigned int* ttbPtr = TTB_BASE + (va >> 20);
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@ sections are 1MB size
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mov r1, r1, lsr #20
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ldr r3, =TTB_BASE_ADDR
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add r1, r3, r1, lsl #0x2
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@ Add MB to pa, flags are already present in pa, but addition
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@ should not effect them
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@
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@ for( ; mb>0; mb--, pa += (1 << 20))
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@ {
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@ *(ttbPtr++) = pa;
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@ }
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cmp r2, #0
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bxle lr
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mov r3, #0x0
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1: @ loop
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str r0, [r1], #4
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add r0, r0, #0x100000
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add r3, r3, #0x1
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cmp r2, r3
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bne 1b @ loop
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bx lr
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.size map_section, .-map_section
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/*
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* void enable_mmu(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global enable_mmu
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.type enable_mmu, %function
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enable_mmu:
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mov r0, #0 @
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLB
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mcr p15, 0, r0, c7, c7,0 @ invalidate both i and dcache
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mrc p15, 0, r0, c1, c0, 0 @
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orr r0, r0, #1 @ enable mmu bit, i and dcache
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orr r0, r0, #1<<2 @ enable dcache
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orr r0, r0, #1<<12 @ enable icache
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mcr p15, 0, r0, c1, c0, 0 @
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nop @
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nop @
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nop @
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nop @
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bx lr @
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.size enable_mmu, .-enable_mmu
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.ltorg
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#endif /* USE_MMU */
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/** Cache coherency **/
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/*
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* Write DCache back to RAM for the given range and remove cache lines
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* from DCache afterwards
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* void commit_discard_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global commit_discard_dcache_range
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.type commit_discard_dcache_range, %function
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.global invalidate_dcache_range @ Alias, deprecated
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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commit_discard_dcache_range:
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invalidate_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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bic r0, r0, #31 @ Align start to cache line (down)
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1: @ inv_start @
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mcr p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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add r0, r0, #32 @
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cmp r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @ inv_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size commit_discard_dcache_range, .-commit_discard_dcache_range
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/*
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* Write DCache back to RAM for the given range
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* void commit_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global commit_dcache_range
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.type commit_dcache_range, %function
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.global clean_dcache_range @ Alias, deprecated
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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commit_dcache_range:
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clean_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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bic r0, r0, #31 @ Align start to cache line (down)
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1: @ clean_start @
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mcr p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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add r0, r0, #32 @
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cmp r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c10, 1 @ Clean line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @clean_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size commit_dcache_range, .-commit_dcache_range
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/*
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* Remove cache lines for the given range from DCache
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void discard_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global discard_dcache_range
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.type discard_dcache_range, %function
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.global dump_dcache_range @ Alias, deprecated
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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discard_dcache_range:
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dump_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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cmp r1, r0 @ end <= start now?
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1: @ discard_start @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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mcrhi p15, 0, r0, c7, c6, 1 @ Invalidate line by MVA
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addhi r0, r0, #32 @
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cmphi r1, r0 @
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bhi 1b @ discard_start @
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size discard_dcache_range, .-discard_dcache_range
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/*
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* Write entire DCache back to RAM
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* void commit_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global commit_dcache
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.type commit_dcache, %function
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.global cpucache_commit @ Alias
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.global clean_dcache @ Alias, deprecated
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.global cpucache_flush @ Alias, deprecated
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commit_dcache:
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cpucache_commit:
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clean_dcache:
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cpucache_flush:
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#ifdef HAVE_TEST_AND_CLEAN_CACHE
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mrc p15, 0, r15, c7, c10, 3 @ test and clean dcache
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bne commit_dcache
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mov r1, #0
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#else
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mov r1, #0x00000000 @
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1: @ commit_start @
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mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index
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add r0, r1, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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.rept INDEX_STEPS - 2 /* 2 steps already executed */
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add r0, r0, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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.endr
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ commit_start @
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#endif /* HAVE_TEST_AND_CLEAN_CACHE */
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size commit_dcache, .-commit_dcache
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/*
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* Commit and discard entire DCache, will do writeback
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* void commit_discard_dcache(void);
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*/
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.section .icode, "ax", %progbits
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.align 2
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.global commit_discard_dcache
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.type commit_discard_dcache, %function
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.global invalidate_dcache @ Alias, deprecated
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commit_discard_dcache:
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invalidate_dcache:
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#ifdef HAVE_TEST_AND_CLEAN_CACHE
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mrc p15, 0, r15, c7, c14, 3 @ test, clean and invalidate dcache
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bne commit_discard_dcache
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mov r1, #0
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#else
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mov r1, #0x00000000 @
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1: @ inv_start @
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mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r1, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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.rept INDEX_STEPS - 2 /* 2 steps already executed */
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add r0, r0, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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.endr
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ inv_start @
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#endif /* HAVE_TEST_AND_CLEAN_CACHE */
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size commit_discard_dcache, .-commit_discard_dcache
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/*
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* Discards the entire ICache, and commit+discards the entire DCache
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* void commit_discard_idcache(void);
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*/
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.section .icode, "ax", %progbits
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.align 2
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.global commit_discard_idcache
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.type commit_discard_idcache, %function
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.global cpucache_commit_discard @ Alias
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.global invalidate_idcache @ Alias, deprecated
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.global cpucache_invalidate @ Alias, deprecated
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commit_discard_idcache:
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cpucache_commit_discard:
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invalidate_idcache:
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cpucache_invalidate:
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mov r2, lr @ save lr to r1, call uses r0 only
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bl commit_discard_dcache @ commit and discard entire DCache
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mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call)
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bx r2
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.size commit_discard_idcache, .-commit_discard_idcache
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