94f7d0f290
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17154 a1c6a512-1295-4272-9138-f99709370657
337 lines
8.9 KiB
C
337 lines
8.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2008 by Michael Sevakis
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "cpu.h"
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#include "spi-imx31.h"
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#include "gpio-imx31.h"
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#include "mc13783.h"
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#include "debug.h"
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#include "kernel.h"
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#include "power-imx31.h"
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#include "button-target.h"
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#include "adc-target.h"
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#include "usb-target.h"
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/* This is all based on communicating with the MC13783 PMU which is on
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* CSPI2 with the chip select at 0. The LCD controller resides on
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* CSPI3 cs1, but we have no idea how to communicate to it */
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static struct spi_node mc13783_spi =
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{
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CSPI2_NUM, /* CSPI module 2 */
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CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */
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CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */
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CSPI_CONREG_DATA_RATE_DIV_4 | /* Clock = IPG_CLK/4 - 16.5MHz */
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CSPI_BITCOUNT(32-1) | /* All 32 bits are to be transferred */
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CSPI_CONREG_SSPOL | /* SS active high */
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CSPI_CONREG_SSCTL | /* Negate SS between SPI bursts */
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CSPI_CONREG_MODE, /* Master mode */
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0, /* SPI clock - no wait states */
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};
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static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
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static const char *mc13783_thread_name = "pmic";
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static struct wakeup mc13783_wake;
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/* The next two functions are rather target-specific but they'll just be left
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* here for the moment */
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static __attribute__((noreturn)) void mc13783_interrupt_thread(void)
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{
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const unsigned char status_regs[2] =
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{
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MC13783_INTERRUPT_STATUS0,
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MC13783_INTERRUPT_STATUS1,
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};
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uint32_t pending[2];
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uint32_t value;
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mc13783_read_regset(status_regs, pending, 2);
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mc13783_write_regset(status_regs, pending, 2);
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gpio_enable_event(MC13783_GPIO_NUM, MC13783_EVENT_ID);
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/* Check initial states for events with a sense bit */
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value = mc13783_read(MC13783_INTERRUPT_SENSE0);
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usb_set_status(value & MC13783_USB4V4);
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set_charger_inserted(value & MC13783_CHGDET);
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value = mc13783_read(MC13783_INTERRUPT_SENSE1);
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button_power_set_state((value & MC13783_ONOFD1) == 0);
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set_headphones_inserted((value & MC13783_ONOFD2) == 0);
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pending[0] = pending[1] = 0xffffff;
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mc13783_write_regset(status_regs, pending, 2);
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/* Enable desired PMIC interrupts - some are unmasked in the drivers that
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* handle a specific task */
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mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_CHGDET);
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mc13783_clear(MC13783_INTERRUPT_MASK1, MC13783_ONOFD1 | MC13783_ONOFD2);
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while (1)
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{
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wakeup_wait(&mc13783_wake, TIMEOUT_BLOCK);
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mc13783_read_regset(status_regs, pending, 2);
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mc13783_write_regset(status_regs, pending, 2);
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if (pending[0])
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{
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/* Handle ...PENDING0 */
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/* Handle interrupts without a sense bit */
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if (pending[0] & MC13783_ADCDONE)
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adc_done();
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/* Handle interrupts that have a sense bit that needs to
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* be checked */
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if (pending[0] & (MC13783_CHGDET | MC13783_USB4V4))
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{
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value = mc13783_read(MC13783_INTERRUPT_SENSE0);
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if (pending[0] & MC13783_CHGDET)
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set_charger_inserted(value & MC13783_CHGDET);
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if (pending[0] & MC13783_USB4V4)
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usb_set_status(value & MC13783_USB4V4);
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}
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}
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if (pending[1])
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{
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/* Handle ...PENDING1 */
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/* Handle interrupts without a sense bit */
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/* ... */
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/* Handle interrupts that have a sense bit that needs to
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* be checked */
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if (pending[1] & (MC13783_ONOFD1 | MC13783_ONOFD2))
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{
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value = mc13783_read(MC13783_INTERRUPT_SENSE1);
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if (pending[1] & MC13783_ONOFD1)
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button_power_set_state((value & MC13783_ONOFD1) == 0);
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if (pending[1] & MC13783_ONOFD2)
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set_headphones_inserted((value & MC13783_ONOFD2) == 0);
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}
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}
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}
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}
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/* GPIO interrupt handler for mc13783 */
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int mc13783_event(void)
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{
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MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
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wakeup_signal(&mc13783_wake);
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return 1; /* Yes, it's handled */
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}
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void mc13783_init(void)
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{
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/* Serial interface must have been initialized first! */
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wakeup_init(&mc13783_wake);
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/* Enable the PMIC SPI module */
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spi_enable_module(&mc13783_spi);
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/* Mask any PMIC interrupts for now - poll initial status in thread
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* and enable them there */
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mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
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mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
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MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
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create_thread(mc13783_interrupt_thread, mc13783_thread_stack,
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sizeof(mc13783_thread_stack), 0, mc13783_thread_name
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IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
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}
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uint32_t mc13783_set(unsigned address, uint32_t bits)
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{
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spi_lock(&mc13783_spi);
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uint32_t data = mc13783_read(address);
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if (data != (uint32_t)-1)
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mc13783_write(address, data | bits);
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spi_unlock(&mc13783_spi);
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return data;
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}
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uint32_t mc13783_clear(unsigned address, uint32_t bits)
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{
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spi_lock(&mc13783_spi);
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uint32_t data = mc13783_read(address);
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if (data != (uint32_t)-1)
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mc13783_write(address, data & ~bits);
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spi_unlock(&mc13783_spi);
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return data;
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}
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int mc13783_write(unsigned address, uint32_t data)
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{
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struct spi_transfer xfer;
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uint32_t packet;
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if (address >= MC13783_NUM_REGS)
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return -1;
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packet = (1 << 31) | (address << 25) | (data & 0xffffff);
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xfer.txbuf = &packet;
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xfer.rxbuf = &packet;
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xfer.count = 1;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return -1;
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return 1 - xfer.count;
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}
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int mc13783_write_multiple(unsigned start, const uint32_t *data, int count)
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{
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int i;
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struct spi_transfer xfer;
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uint32_t packets[MC13783_NUM_REGS];
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if (start + count > MC13783_NUM_REGS)
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return -1;
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/* Prepare payload */
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for (i = 0; i < count; i++, start++)
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{
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packets[i] = (1 << 31) | (start << 25) | (data[i] & 0xffffff);
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}
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xfer.txbuf = packets;
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xfer.rxbuf = packets;
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xfer.count = count;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return -1;
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return count - xfer.count;
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}
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int mc13783_write_regset(const unsigned char *regs, const uint32_t *data,
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int count)
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{
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int i;
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struct spi_transfer xfer;
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uint32_t packets[MC13783_NUM_REGS];
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if (count > MC13783_NUM_REGS)
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return -1;
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for (i = 0; i < count; i++)
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{
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uint32_t reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return -1;
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packets[i] = (1 << 31) | (reg << 25) | (data[i] & 0xffffff);
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}
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xfer.txbuf = packets;
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xfer.rxbuf = packets;
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xfer.count = count;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return -1;
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return count - xfer.count;
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}
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uint32_t mc13783_read(unsigned address)
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{
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uint32_t packet;
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struct spi_transfer xfer;
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if (address >= MC13783_NUM_REGS)
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return (uint32_t)-1;
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packet = address << 25;
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xfer.txbuf = &packet;
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xfer.rxbuf = &packet;
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xfer.count = 1;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return (uint32_t)-1;
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return packet;
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}
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int mc13783_read_multiple(unsigned start, uint32_t *buffer, int count)
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{
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int i;
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struct spi_transfer xfer;
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if (start + count > MC13783_NUM_REGS)
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return -1;
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xfer.txbuf = buffer;
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xfer.rxbuf = buffer;
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xfer.count = count;
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/* Prepare TX payload */
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for (i = 0; i < count; i++, start++)
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buffer[i] = start << 25;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return -1;
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return count - xfer.count;
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}
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int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer,
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int count)
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{
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int i;
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struct spi_transfer xfer;
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if (count > MC13783_NUM_REGS)
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return -1;
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for (i = 0; i < count; i++)
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{
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unsigned reg = regs[i];
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if (reg >= MC13783_NUM_REGS)
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return -1;
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buffer[i] = reg << 25;
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}
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xfer.txbuf = buffer;
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xfer.rxbuf = buffer;
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xfer.count = count;
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if (!spi_transfer(&mc13783_spi, &xfer))
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return -1;
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return count - xfer.count;
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}
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