934514558b
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24142 a1c6a512-1295-4272-9138-f99709370657
134 lines
No EOL
4.6 KiB
ArmAsm
134 lines
No EOL
4.6 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Jens Arnold
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* Copyright (C) 2009 by Andrew Mahone
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*
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* Optimised unsigned integer division for ARMv4
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*
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* Based on: libgcc routines for ARM cpu.
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* Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
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* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
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* Free Software Foundation, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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/* Codecs should not normally do this, but we need to check a macro, and
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* codecs.h would confuse the assembler. */
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/* Adapted from an algorithm given in ARM System Developer's Guide (7.3.1.2)
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for dividing a 30-bit value by a 15-bit value, with two operations per
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iteration by storing quotient and remainder together and adding the previous
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quotient bit during trial subtraction. Modified to work with any dividend
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and divisor both less than 1 << 30, and skipping trials by calculating bits
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in output.
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*/
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.macro ARM_DIV_31_BODY dividend, divisor, result, bits, curbit, quotient
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mov \bits, #1
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cmp \divisor, \dividend, lsr #16
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movls \divisor, \divisor, lsl #16
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addls \bits, \bits, #16
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cmp \divisor, \dividend, lsr #8
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movls \divisor, \divisor, lsl #8
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addls \bits, \bits, #8
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cmp \divisor, \dividend, lsr #4
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movls \divisor, \divisor, lsl #4
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addls \bits, \bits, #4
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cmp \divisor, \dividend, lsr #2
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movls \divisor, \divisor, lsl #2
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addls \bits, \bits, #2
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cmp \divisor, \dividend, lsr #1
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movls \divisor, \divisor, lsl #1
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addls \bits, \bits, #1
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rsb \divisor, \divisor, #0
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adds \result, \dividend, \divisor
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subcc \result, \result, \divisor
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rsb \curbit, \bits, #31
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add pc, pc, \curbit, lsl #3
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nop
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.rept 30
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adcs \result, \divisor, \result, lsl #1
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subcc \result, \result, \divisor
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.endr
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/* shift remainder/quotient left one, add final quotient bit */
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adc \result, \result, \result
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mov \dividend, \result, lsr \bits
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eor \quotient, \result, \dividend, lsl \bits
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.endm
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.macro ARM_DIV_32_BODY dividend, divisor, result, curbit
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mov \result, \dividend
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mov \curbit, #90 @ 3 * 30, (calculating branch dest)
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cmp \divisor, \result, lsr #16
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movls \result,\result, lsr #16
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subls \curbit, \curbit, #48
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cmp \divisor, \result, lsr #8
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movls \result,\result, lsr #8
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subls \curbit, \curbit, #24
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cmp \divisor, \result, lsr #4
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movls \result,\result, lsr #4
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subls \curbit, \curbit, #12
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cmp \divisor, \result, lsr #2
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subls \curbit, \curbit, #6
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@ Calculation is only done down to shift=2, because the shift=1 step
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@ would need 3 more cycles, but would only gain 1.5 cycles on average.
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mov \result, #0
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add pc, pc, \curbit, lsl #2
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nop
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.set shift, 32
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.rept 31
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.set shift, shift - 1
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cmp \divisor, \dividend, lsr #shift
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orrls \result, \result, #(1 << shift)
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subls \dividend, \dividend, \divisor, lsl #shift
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.endr @ shift==0 in the .rept would cause a warning for lsr #0
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cmp \divisor, \dividend
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orrls \result, \result, #1
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@subls \dividend, \dividend, \divisor @ correct remainder not needed
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.endm
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#ifdef USE_IRAM
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.section .icode,"ax",%progbits
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#else
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.text
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#endif
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.align
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.global udiv32_arm
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.type udiv32_arm,%function
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udiv32_arm:
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cmp r1, #0
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beq 20f
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tst r0, r0
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/* High bit must be unset, otherwise use ARM_DIV_32_BODY. High bit of
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divisor is also unset dividend has been tested to be >= divisor.
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*/
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bmi 10f
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ARM_DIV_31_BODY r0, r1, r2, r3, ip, r0
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bx lr
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10:
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ARM_DIV_32_BODY r0, r1, r2, r3
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mov r0, r2
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bx lr
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20:
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movne r0, #0
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bx lr |