149 lines
4.9 KiB
C
149 lines
4.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_DDRC_H__
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#define __HEADERGEN_DDRC_H__
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#include "macro.h"
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#define REG_DDRC_STATUS jz_reg(DDRC_STATUS)
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#define JA_DDRC_STATUS (0xb34f0000 + 0x0)
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#define JT_DDRC_STATUS JIO_32_RW
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#define JN_DDRC_STATUS DDRC_STATUS
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#define JI_DDRC_STATUS
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#define REG_DDRC_CFG jz_reg(DDRC_CFG)
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#define JA_DDRC_CFG (0xb34f0000 + 0x4)
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#define JT_DDRC_CFG JIO_32_RW
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#define JN_DDRC_CFG DDRC_CFG
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#define JI_DDRC_CFG
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#define REG_DDRC_CTRL jz_reg(DDRC_CTRL)
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#define JA_DDRC_CTRL (0xb34f0000 + 0x8)
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#define JT_DDRC_CTRL JIO_32_RW
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#define JN_DDRC_CTRL DDRC_CTRL
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#define JI_DDRC_CTRL
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#define REG_DDRC_TIMING1 jz_reg(DDRC_TIMING1)
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#define JA_DDRC_TIMING1 (0xb34f0000 + 0x60)
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#define JT_DDRC_TIMING1 JIO_32_RW
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#define JN_DDRC_TIMING1 DDRC_TIMING1
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#define JI_DDRC_TIMING1
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#define REG_DDRC_TIMING2 jz_reg(DDRC_TIMING2)
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#define JA_DDRC_TIMING2 (0xb34f0000 + 0x64)
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#define JT_DDRC_TIMING2 JIO_32_RW
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#define JN_DDRC_TIMING2 DDRC_TIMING2
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#define JI_DDRC_TIMING2
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#define REG_DDRC_TIMING3 jz_reg(DDRC_TIMING3)
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#define JA_DDRC_TIMING3 (0xb34f0000 + 0x68)
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#define JT_DDRC_TIMING3 JIO_32_RW
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#define JN_DDRC_TIMING3 DDRC_TIMING3
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#define JI_DDRC_TIMING3
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#define REG_DDRC_TIMING4 jz_reg(DDRC_TIMING4)
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#define JA_DDRC_TIMING4 (0xb34f0000 + 0x6c)
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#define JT_DDRC_TIMING4 JIO_32_RW
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#define JN_DDRC_TIMING4 DDRC_TIMING4
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#define JI_DDRC_TIMING4
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#define REG_DDRC_TIMING5 jz_reg(DDRC_TIMING5)
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#define JA_DDRC_TIMING5 (0xb34f0000 + 0x70)
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#define JT_DDRC_TIMING5 JIO_32_RW
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#define JN_DDRC_TIMING5 DDRC_TIMING5
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#define JI_DDRC_TIMING5
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#define REG_DDRC_TIMING6 jz_reg(DDRC_TIMING6)
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#define JA_DDRC_TIMING6 (0xb34f0000 + 0x74)
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#define JT_DDRC_TIMING6 JIO_32_RW
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#define JN_DDRC_TIMING6 DDRC_TIMING6
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#define JI_DDRC_TIMING6
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#define REG_DDRC_REFCNT jz_reg(DDRC_REFCNT)
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#define JA_DDRC_REFCNT (0xb34f0000 + 0x18)
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#define JT_DDRC_REFCNT JIO_32_RW
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#define JN_DDRC_REFCNT DDRC_REFCNT
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#define JI_DDRC_REFCNT
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#define REG_DDRC_MMAP0 jz_reg(DDRC_MMAP0)
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#define JA_DDRC_MMAP0 (0xb34f0000 + 0x24)
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#define JT_DDRC_MMAP0 JIO_32_RW
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#define JN_DDRC_MMAP0 DDRC_MMAP0
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#define JI_DDRC_MMAP0
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#define REG_DDRC_MMAP1 jz_reg(DDRC_MMAP1)
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#define JA_DDRC_MMAP1 (0xb34f0000 + 0x28)
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#define JT_DDRC_MMAP1 JIO_32_RW
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#define JN_DDRC_MMAP1 DDRC_MMAP1
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#define JI_DDRC_MMAP1
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#define REG_DDRC_DLP jz_reg(DDRC_DLP)
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#define JA_DDRC_DLP (0xb34f0000 + 0xbc)
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#define JT_DDRC_DLP JIO_32_RW
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#define JN_DDRC_DLP DDRC_DLP
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#define JI_DDRC_DLP
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#define REG_DDRC_REMAP1 jz_reg(DDRC_REMAP1)
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#define JA_DDRC_REMAP1 (0xb34f0000 + 0x9c)
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#define JT_DDRC_REMAP1 JIO_32_RW
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#define JN_DDRC_REMAP1 DDRC_REMAP1
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#define JI_DDRC_REMAP1
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#define REG_DDRC_REMAP2 jz_reg(DDRC_REMAP2)
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#define JA_DDRC_REMAP2 (0xb34f0000 + 0xa0)
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#define JT_DDRC_REMAP2 JIO_32_RW
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#define JN_DDRC_REMAP2 DDRC_REMAP2
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#define JI_DDRC_REMAP2
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#define REG_DDRC_REMAP3 jz_reg(DDRC_REMAP3)
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#define JA_DDRC_REMAP3 (0xb34f0000 + 0xa4)
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#define JT_DDRC_REMAP3 JIO_32_RW
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#define JN_DDRC_REMAP3 DDRC_REMAP3
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#define JI_DDRC_REMAP3
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#define REG_DDRC_REMAP4 jz_reg(DDRC_REMAP4)
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#define JA_DDRC_REMAP4 (0xb34f0000 + 0xa8)
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#define JT_DDRC_REMAP4 JIO_32_RW
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#define JN_DDRC_REMAP4 DDRC_REMAP4
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#define JI_DDRC_REMAP4
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#define REG_DDRC_REMAP5 jz_reg(DDRC_REMAP5)
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#define JA_DDRC_REMAP5 (0xb34f0000 + 0xac)
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#define JT_DDRC_REMAP5 JIO_32_RW
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#define JN_DDRC_REMAP5 DDRC_REMAP5
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#define JI_DDRC_REMAP5
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#define REG_DDRC_AUTOSR_CNT jz_reg(DDRC_AUTOSR_CNT)
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#define JA_DDRC_AUTOSR_CNT (0xb34f0000 + 0x308)
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#define JT_DDRC_AUTOSR_CNT JIO_32_RW
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#define JN_DDRC_AUTOSR_CNT DDRC_AUTOSR_CNT
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#define JI_DDRC_AUTOSR_CNT
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#define REG_DDRC_AUTOSR_EN jz_reg(DDRC_AUTOSR_EN)
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#define JA_DDRC_AUTOSR_EN (0xb34f0000 + 0x304)
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#define JT_DDRC_AUTOSR_EN JIO_32_RW
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#define JN_DDRC_AUTOSR_EN DDRC_AUTOSR_EN
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#define JI_DDRC_AUTOSR_EN
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#endif /* __HEADERGEN_DDRC_H__*/
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