359 lines
17 KiB
C
359 lines
17 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_AIC_H__
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#define __HEADERGEN_AIC_H__
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#include "macro.h"
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#define REG_AIC_CFG jz_reg(AIC_CFG)
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#define JA_AIC_CFG (0xb0020000 + 0x0)
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#define JT_AIC_CFG JIO_32_RW
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#define JN_AIC_CFG AIC_CFG
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#define JI_AIC_CFG
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#define BP_AIC_CFG_RFTH 24
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#define BM_AIC_CFG_RFTH 0xf000000
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#define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24)
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#define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH
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#define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e)
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#define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH
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#define BP_AIC_CFG_TFTH 16
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#define BM_AIC_CFG_TFTH 0x1f0000
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#define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16)
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#define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH
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#define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e)
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#define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH
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#define BP_AIC_CFG_MSB 12
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#define BM_AIC_CFG_MSB 0x1000
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#define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12)
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#define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB
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#define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e)
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#define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB
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#define BP_AIC_CFG_IBCKD 10
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#define BM_AIC_CFG_IBCKD 0x400
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#define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10)
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#define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD
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#define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e)
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#define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD
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#define BP_AIC_CFG_ISYNCD 9
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#define BM_AIC_CFG_ISYNCD 0x200
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#define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9)
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#define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD
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#define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e)
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#define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD
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#define BP_AIC_CFG_DMODE 8
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#define BM_AIC_CFG_DMODE 0x100
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#define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8)
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#define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE
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#define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e)
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#define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE
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#define BP_AIC_CFG_CDC_SLAVE 7
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#define BM_AIC_CFG_CDC_SLAVE 0x80
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#define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7)
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#define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE
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#define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e)
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#define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE
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#define BP_AIC_CFG_LSMP 6
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#define BM_AIC_CFG_LSMP 0x40
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#define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6)
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#define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP
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#define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e)
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#define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP
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#define BP_AIC_CFG_ICDC 5
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#define BM_AIC_CFG_ICDC 0x20
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#define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5)
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#define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC
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#define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e)
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#define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC
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#define BP_AIC_CFG_AUSEL 4
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#define BM_AIC_CFG_AUSEL 0x10
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#define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4)
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#define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL
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#define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e)
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#define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL
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#define BP_AIC_CFG_RST 3
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#define BM_AIC_CFG_RST 0x8
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#define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3)
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#define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST
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#define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e)
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#define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST
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#define BP_AIC_CFG_BCKD 2
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#define BM_AIC_CFG_BCKD 0x4
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#define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2)
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#define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD
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#define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e)
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#define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD
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#define BP_AIC_CFG_SYNCD 1
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#define BM_AIC_CFG_SYNCD 0x2
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#define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1)
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#define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD
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#define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e)
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#define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD
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#define BP_AIC_CFG_ENABLE 0
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#define BM_AIC_CFG_ENABLE 0x1
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#define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0)
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#define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE
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#define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e)
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#define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE
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#define REG_AIC_CCR jz_reg(AIC_CCR)
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#define JA_AIC_CCR (0xb0020000 + 0x4)
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#define JT_AIC_CCR JIO_32_RW
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#define JN_AIC_CCR AIC_CCR
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#define JI_AIC_CCR
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#define BP_AIC_CCR_CHANNEL 24
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#define BM_AIC_CCR_CHANNEL 0x7000000
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#define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24)
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#define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL
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#define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e)
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#define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL
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#define BP_AIC_CCR_OSS 19
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#define BM_AIC_CCR_OSS 0x380000
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#define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19)
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#define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS
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#define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e)
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#define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS
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#define BP_AIC_CCR_ISS 16
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#define BM_AIC_CCR_ISS 0x70000
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#define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16)
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#define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS
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#define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e)
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#define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS
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#define BP_AIC_CCR_PACK16 28
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#define BM_AIC_CCR_PACK16 0x10000000
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#define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28)
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#define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16
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#define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e)
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#define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16
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#define BP_AIC_CCR_RDMS 15
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#define BM_AIC_CCR_RDMS 0x8000
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#define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15)
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#define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS
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#define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e)
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#define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS
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#define BP_AIC_CCR_TDMS 14
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#define BM_AIC_CCR_TDMS 0x4000
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#define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14)
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#define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS
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#define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e)
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#define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS
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#define BP_AIC_CCR_M2S 11
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#define BM_AIC_CCR_M2S 0x800
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#define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11)
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#define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S
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#define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e)
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#define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S
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#define BP_AIC_CCR_ENDSW 10
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#define BM_AIC_CCR_ENDSW 0x400
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#define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10)
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#define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW
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#define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e)
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#define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW
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#define BP_AIC_CCR_ASVTSU 9
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#define BM_AIC_CCR_ASVTSU 0x200
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#define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9)
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#define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU
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#define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e)
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#define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU
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#define BP_AIC_CCR_TFLUSH 8
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#define BM_AIC_CCR_TFLUSH 0x100
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#define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8)
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#define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH
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#define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e)
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#define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH
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#define BP_AIC_CCR_RFLUSH 7
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#define BM_AIC_CCR_RFLUSH 0x80
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#define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7)
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#define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH
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#define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e)
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#define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH
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#define BP_AIC_CCR_EROR 6
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#define BM_AIC_CCR_EROR 0x40
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#define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6)
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#define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR
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#define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e)
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#define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR
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#define BP_AIC_CCR_ETUR 5
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#define BM_AIC_CCR_ETUR 0x20
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#define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5)
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#define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR
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#define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e)
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#define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR
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#define BP_AIC_CCR_ERFS 4
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#define BM_AIC_CCR_ERFS 0x10
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#define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4)
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#define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS
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#define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e)
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#define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS
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#define BP_AIC_CCR_ETFS 3
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#define BM_AIC_CCR_ETFS 0x8
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#define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3)
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#define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS
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#define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e)
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#define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS
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#define BP_AIC_CCR_ENLBF 2
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#define BM_AIC_CCR_ENLBF 0x4
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#define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2)
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#define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF
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#define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e)
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#define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF
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#define BP_AIC_CCR_ERPL 1
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#define BM_AIC_CCR_ERPL 0x2
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#define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1)
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#define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL
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#define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e)
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#define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL
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#define BP_AIC_CCR_EREC 0
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#define BM_AIC_CCR_EREC 0x1
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#define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0)
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#define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC
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#define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e)
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#define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC
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#define REG_AIC_I2SCR jz_reg(AIC_I2SCR)
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#define JA_AIC_I2SCR (0xb0020000 + 0x10)
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#define JT_AIC_I2SCR JIO_32_RW
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#define JN_AIC_I2SCR AIC_I2SCR
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#define JI_AIC_I2SCR
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#define BP_AIC_I2SCR_RFIRST 17
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#define BM_AIC_I2SCR_RFIRST 0x20000
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#define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17)
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#define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST
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#define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e)
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#define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST
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#define BP_AIC_I2SCR_SWLH 16
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#define BM_AIC_I2SCR_SWLH 0x10000
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#define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16)
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#define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH
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#define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e)
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#define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH
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#define BP_AIC_I2SCR_ISTPBK 13
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#define BM_AIC_I2SCR_ISTPBK 0x2000
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#define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13)
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#define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK
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#define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e)
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#define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK
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#define BP_AIC_I2SCR_STPBK 12
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#define BM_AIC_I2SCR_STPBK 0x1000
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#define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12)
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#define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK
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#define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e)
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#define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK
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#define BP_AIC_I2SCR_ESCLK 4
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#define BM_AIC_I2SCR_ESCLK 0x10
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#define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4)
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#define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK
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#define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e)
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#define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK
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#define BP_AIC_I2SCR_AMSL 0
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#define BM_AIC_I2SCR_AMSL 0x1
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#define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0)
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#define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL
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#define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e)
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#define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL
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#define REG_AIC_SR jz_reg(AIC_SR)
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#define JA_AIC_SR (0xb0020000 + 0x14)
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#define JT_AIC_SR JIO_32_RW
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#define JN_AIC_SR AIC_SR
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#define JI_AIC_SR
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#define BP_AIC_SR_RFL 24
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#define BM_AIC_SR_RFL 0x3f000000
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#define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24)
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#define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL
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#define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e)
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#define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL
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#define BP_AIC_SR_TFL 8
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#define BM_AIC_SR_TFL 0x3f00
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#define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8)
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#define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL
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#define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e)
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#define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL
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#define BP_AIC_SR_ROR 6
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#define BM_AIC_SR_ROR 0x40
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#define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6)
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#define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR
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#define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e)
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#define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR
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#define BP_AIC_SR_TUR 5
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#define BM_AIC_SR_TUR 0x20
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#define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5)
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#define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR
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#define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e)
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#define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR
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#define BP_AIC_SR_RFS 4
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#define BM_AIC_SR_RFS 0x10
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#define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4)
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#define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS
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#define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e)
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#define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS
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#define BP_AIC_SR_TFS 3
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#define BM_AIC_SR_TFS 0x8
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#define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3)
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#define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS
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#define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e)
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#define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS
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#define REG_AIC_I2SSR jz_reg(AIC_I2SSR)
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#define JA_AIC_I2SSR (0xb0020000 + 0x1c)
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#define JT_AIC_I2SSR JIO_32_RW
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#define JN_AIC_I2SSR AIC_I2SSR
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#define JI_AIC_I2SSR
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#define BP_AIC_I2SSR_CHBSY 5
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#define BM_AIC_I2SSR_CHBSY 0x20
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#define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5)
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#define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY
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#define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e)
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#define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY
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#define BP_AIC_I2SSR_TBSY 4
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#define BM_AIC_I2SSR_TBSY 0x10
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#define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4)
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#define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY
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#define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e)
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#define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY
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#define BP_AIC_I2SSR_RBSY 3
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#define BM_AIC_I2SSR_RBSY 0x8
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#define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3)
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#define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY
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#define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e)
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#define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY
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#define BP_AIC_I2SSR_BSY 2
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#define BM_AIC_I2SSR_BSY 0x4
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#define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2)
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#define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY
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#define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e)
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#define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY
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#define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV)
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#define JA_AIC_I2SDIV (0xb0020000 + 0x30)
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#define JT_AIC_I2SDIV JIO_32_RW
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#define JN_AIC_I2SDIV AIC_I2SDIV
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#define JI_AIC_I2SDIV
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#define REG_AIC_DR jz_reg(AIC_DR)
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#define JA_AIC_DR (0xb0020000 + 0x34)
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#define JT_AIC_DR JIO_32_RW
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#define JN_AIC_DR AIC_DR
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#define JI_AIC_DR
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#endif /* __HEADERGEN_AIC_H__*/
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