Aidan MacDonald 8cb4c18310 Really fix the MIPS cache bug this time ... In fixing the original bug I tried to optimize discard_dcache_range() to minimize writeback and inadvertently introduced a second bug, which typically ends in a TLB refill panic. It occurs only if the range fits within one cache line, and when both the start and end of the range are not aligned to a cache line. This causes ptr to be incremented and end to be decremented, so ptr > end, and the loop can't terminate. Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65		2021-03-03 23:57:08 +00:00
..
ingenic_jz47xx	Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPS	2021-03-03 20:50:28 +00:00
mmu-mips.c	Really fix the MIPS cache bug this time	2021-03-03 23:57:08 +00:00
mmu-mips.h	mips: Heavily rework DMA & caching code	2020-09-03 15:34:28 -04:00