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rockbox/firmware/target/arm/pcm-pp.c
Dave Chapman 1092edf3e1 Packed I2S for ipod Color (tested) and ipod 4G (untested, but assumed to be the same as the Color - everything else is). 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15053 a1c6a512-1295-4272-9138-f99709370657
2007-10-09 20:57:31 +00:00

597 lines
17 KiB
C
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2006 by Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include <stdlib.h>
#include "system.h"
#include "kernel.h"
#include "logf.h"
#include "audio.h"
#include "sound.h"
/** DMA **/
/* List of transfer settings. Defined by player in order to have an inventory
of working settings. DMA-compatible settings should be found for here, i2s,
and codec setup using "arithmetic" the hardware supports like halfword
swapping. Try to use 32-bit packed in IIS modes if possible. */
#if defined(SANSA_C200) || defined(SANSA_E200) \
|| defined(IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_NANO) \
|| defined(IPOD_VIDEO) || defined(IPOD_MINI2G) \
|| defined(IPOD_COLOR) || defined(IPOD_4G)
/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
#define SAMPLE_SIZE 16
#define TRANSFER_SIZE 32
#elif 0
/* 16-bit, one left 16-bit sample followed by one right 16-bit sample */
#define SAMPLE_SIZE 16
#define TRANSFER_SIZE 16
#else
/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
#define SAMPLE_SIZE 32
#define TRANSFER_SIZE 32
#endif
struct dma_data
{
/* NOTE: The order of size and p is important if you use assembler
optimised fiq handler, so don't change it. */
#if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
uint16_t *p;
#elif TRANSFER_SIZE == 32
uint32_t *p;
#endif
#elif SAMPLE_SIZE == 32
uint16_t *p;
#endif
size_t size;
#if NUM_CORES > 1
unsigned core;
#endif
int locked;
int state;
};
extern void *fiq_function;
/* Dispatch to the proper handler and leave the main vector table alone */
void fiq_handler(void) ICODE_ATTR __attribute__((naked));
void fiq_handler(void)
{
asm volatile (
"ldr pc, [pc, #-4] \n"
"fiq_function: \n"
".word 0 \n"
);
}
/* TODO: Get simultaneous recording and playback to work. Just needs some tweaking */
/****************************************************************************
** Playback DMA transfer
**/
struct dma_data dma_play_data NOCACHEBSS_ATTR =
{
/* Initialize to a locked, stopped state */
.p = NULL,
.size = 0,
#if NUM_CORES > 1
.core = 0x00,
#endif
.locked = 0,
.state = 0
};
static unsigned long pcm_freq NOCACHEDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
void pcm_set_frequency(unsigned int frequency)
{
(void)frequency;
pcm_freq = HW_SAMPR_DEFAULT;
}
void pcm_apply_settings(void)
{
pcm_curr_sampr = pcm_freq;
}
/* ASM optimised FIQ handler. GCC fails to make use of the fact that FIQ mode
has registers r8-r14 banked, and so does not need to be saved. This routine
uses only these registers, and so will never touch the stack unless it
actually needs to do so when calling pcm_callback_for_more. C version is
still included below for reference and testing.
*/
#if 1
void fiq_playback(void) ICODE_ATTR __attribute__((naked));
void fiq_playback(void)
{
/* r10 contains IISCONFIG address (set in crt0.S to minimise code in actual
* FIQ handler. r11 contains address of p (also set in crt0.S). Most other
* addresses we need are generated by using offsets with these two.
* r10 + 0x40 is IISFIFO_WR, and r10 + 0x0c is IISFIFO_CFG.
* r8 and r9 contains local copies of p and size respectively.
* r12 is a working register.
*/
asm volatile (
#if CONFIG_CPU == PP5002
"ldr r12, =0xcf001040 \n" /* Some magic from iPodLinux */
"ldr r12, [r12] \n"
#endif
"ldmia r11, { r8-r9 } \n" /* r8 = p, r9 = size */
"cmp r9, #0 \n" /* is size 0? */
"beq .more_data \n" /* if so, ask pcmbuf for more data */
".fifo_loop: \n"
"ldr r12, [r10, %[cfg]] \n" /* read IISFIFO_CFG to check FIFO status */
"ands r12, r12, %[mask] \n"
"beq .exit \n" /* FIFO full, exit */
#if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
"ldrh r12, [r8], #2 \n" /* Load left channel */
"strh r12, [r10, %[wr]] \n" /* Store it */
"ldrh r12, [r8], #2 \n" /* Load right channel */
"strh r12, [r10, %[wr]] \n" /* Store it */
#elif TRANSFER_SIZE == 32
"ldr r12, [r8], #4 \n" /* load two samples */
"str r12, [r10, %[wr]] \n" /* write them */
#endif
#elif SAMPLE_SIZE == 32
"ldr r12, [r8], #4 \n" /* load two samples */
"mov r12, r12, ror #16 \n" /* put left sample at the top bits */
"str r12, [r10, %[wr]] \n" /* write top sample, lower sample ignored */
"mov r12, r12, lsl #16 \n" /* shift lower sample up */
"str r12, [r10, %[wr]] \n" /* then write it */
#endif
"subs r9, r9, #4 \n" /* check if we have more samples */
"bne .fifo_loop \n" /* yes, continue */
".more_data: \n"
"stmfd sp!, { r0-r3, lr } \n" /* stack scratch regs and lr */
"ldr r2, =pcm_callback_for_more \n"
"ldr r2, [r2] \n" /* get callback address */
"cmp r2, #0 \n" /* check for null pointer */
"stmneia r11, { r8-r9 } \n" /* save internal copies of variables back */
"movne r0, r11 \n" /* r0 = &p */
"addne r1, r11, #4 \n" /* r1 = &size */
"movne lr, pc \n" /* call pcm_callback_for_more */
"bxne r2 \n"
"ldmia r11, { r8-r9 } \n" /* reload p and size */
"cmp r9, #0 \n" /* did we actually get more data? */
"ldmnefd sp!, { r0-r3, lr } \n"
"bne .fifo_loop \n" /* yes, continue to try feeding FIFO */
"ldr r12, =pcm_play_dma_stop \n"
"mov lr, pc \n"
"bx r12 \n"
"ldr r12, =pcm_play_dma_stopped_callback \n"
"mov lr, pc \n"
"bx r12 \n"
"ldmfd sp!, { r0-r3, lr } \n"
".exit: \n" /* (r8=0 if stopping, look above) */
"stmia r11, { r8-r9 } \n" /* save p and size */
"subs pc, lr, #4 \n" /* FIQ specific return sequence */
".ltorg \n"
: /* These must only be integers! No regs */
: [mask]"i"(IIS_TX_FREE_MASK & (IIS_TX_FREE_MASK-1)),
[cfg]"i"((int)&IISFIFO_CFG - (int)&IISCONFIG),
[wr]"i"((int)&IISFIFO_WR - (int)&IISCONFIG)
);
}
#else /* C version for reference */
void fiq_playback(void) __attribute__((interrupt ("FIQ"))) ICODE_ATTR;
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void fiq_playback(void)
{
register pcm_more_callback_type get_more;
#if CONFIG_CPU == PP5002
inl(0xcf001040);
#endif
do {
while (dma_play_data.size > 0) {
if (IIS_TX_FREE_COUNT < 2) {
return;
}
#if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
IISFIFO_WRH = *dma_play_data.p++;
IISFIFO_WRH = *dma_play_data.p++;
#elif TRANSFER_SIZE == 32
IISFIFO_WR = *dma_play_data.p++;
#endif
#elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p++ << 16;
IISFIFO_WR = *dma_play_data.p++ << 16;
#endif
dma_play_data.size -= 4;
}
/* p is empty, get some more data */
get_more = pcm_callback_for_more;
if (get_more) {
get_more((unsigned char**)&dma_play_data.p,
&dma_play_data.size);
}
} while (dma_play_data.size);
/* No more data, so disable the FIFO/interrupt */
pcm_play_dma_stop();
pcm_play_dma_stopped_callback();
}
#endif /* ASM / C selection */
/* For the locks, FIQ must be disabled because the handler manipulates
IISCONFIG and the operation is not atomic - dual core support
will require other measures */
void pcm_play_lock(void)
{
int status = set_fiq_status(FIQ_DISABLED);
if (++dma_play_data.locked == 1) {
IIS_IRQTX_REG &= ~IIS_IRQTX;
}
set_fiq_status(status);
}
void pcm_play_unlock(void)
{
int status = set_fiq_status(FIQ_DISABLED);
if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
IIS_IRQTX_REG |= IIS_IRQTX;
}
set_fiq_status(status);
}
static void play_start_pcm(void)
{
fiq_function = fiq_playback;
pcm_apply_settings();
IISCONFIG &= ~IIS_TXFIFOEN; /* Stop transmitting */
dma_play_data.state = 1;
/* Fill the FIFO or start when data is used up */
while (1) {
if (IIS_TX_FREE_COUNT < 2 || dma_play_data.size == 0) {
IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
return;
}
#if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
IISFIFO_WRH = *dma_play_data.p++;
IISFIFO_WRH = *dma_play_data.p++;
#elif TRANSFER_SIZE == 32
IISFIFO_WR = *dma_play_data.p++;
#endif
#elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p++ << 16;
IISFIFO_WR = *dma_play_data.p++ << 16;
#endif
dma_play_data.size -= 4;
}
}
static void play_stop_pcm(void)
{
/* Disable TX interrupt */
IIS_IRQTX_REG &= ~IIS_IRQTX;
dma_play_data.state = 0;
}
void pcm_play_dma_start(const void *addr, size_t size)
{
dma_play_data.p = (void *)(((uintptr_t)addr + 2) & ~3);
dma_play_data.size = (size & ~3);
#if NUM_CORES > 1
/* This will become more important later - and different ! */
dma_play_data.core = processor_id(); /* save initiating core */
#endif
CPU_INT_PRIORITY |= IIS_MASK; /* FIQ priority for I2S */
CPU_INT_EN = IIS_MASK;
play_start_pcm();
}
/* Stops the DMA transfer and interrupt */
void pcm_play_dma_stop(void)
{
play_stop_pcm();
dma_play_data.size = 0;
#if NUM_CORES > 1
dma_play_data.core = 0; /* no core in control */
#endif
}
void pcm_play_dma_pause(bool pause)
{
if (pause) {
play_stop_pcm();
} else {
play_start_pcm();
}
}
size_t pcm_get_bytes_waiting(void)
{
return dma_play_data.size & ~3;
}
void pcm_play_dma_init(void)
{
pcm_set_frequency(SAMPR_44);
/* Initialize default register values. */
audiohw_init();
#ifndef HAVE_WM8731
/* Power on */
audiohw_enable_output(true);
/* Unmute the master channel (DAC should be at zero point now). */
audiohw_mute(false);
#endif
dma_play_data.size = 0;
#if NUM_CORES > 1
dma_play_data.core = 0; /* no core in control */
#endif
IISCONFIG |= IIS_TXFIFOEN;
}
void pcm_postinit(void)
{
audiohw_postinit();
pcm_apply_settings();
}
const void * pcm_play_dma_get_peak_buffer(int *count)
{
unsigned long addr = (unsigned long)dma_play_data.p;
size_t cnt = dma_play_data.size;
*count = cnt >> 2;
return (void *)((addr + 2) & ~3);
}
/****************************************************************************
** Recording DMA transfer
**/
#ifdef HAVE_RECORDING
/* PCM recording interrupt routine lockout */
static struct dma_data dma_rec_data NOCACHEBSS_ATTR =
{
/* Initialize to a locked, stopped state */
.p = NULL,
.size = 0,
#if NUM_CORES > 1
.core = 0x00,
#endif
.locked = 0,
.state = 0
};
/* For the locks, FIQ must be disabled because the handler manipulates
IISCONFIG and the operation is not atomic - dual core support
will require other measures */
void pcm_rec_lock(void)
{
int status = set_fiq_status(FIQ_DISABLED);
if (++dma_rec_data.locked == 1)
IIS_IRQRX_REG &= ~IIS_IRQRX;
set_fiq_status(status);
}
void pcm_rec_unlock(void)
{
int status = set_fiq_status(FIQ_DISABLED);
if (--dma_rec_data.locked == 0 && dma_rec_data.state != 0)
IIS_IRQRX_REG |= IIS_IRQRX;
set_fiq_status(status);
}
/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
void fiq_record(void) ICODE_ATTR __attribute__((interrupt ("FIQ")));
#if defined(SANSA_C200) || defined(SANSA_E200)
void fiq_record(void)
{
register pcm_more_callback_type2 more_ready;
register int32_t value;
if (audio_channels == 2) {
/* RX is stereo */
while (dma_rec_data.size > 0) {
if (IIS_RX_FULL_COUNT < 2) {
return;
}
/* Discard every other sample since ADC clock is 1/2 LRCK */
value = IISFIFO_RD;
IISFIFO_RD;
*dma_rec_data.p++ = value;
dma_rec_data.size -= 4;
/* TODO: Figure out how to do IIS loopback */
if (audio_output_source != AUDIO_SRC_PLAYBACK) {
if (IIS_TX_FREE_COUNT >= 16) {
/* Resync the output FIFO - it ran dry */
IISFIFO_WR = 0;
IISFIFO_WR = 0;
}
IISFIFO_WR = value;
IISFIFO_WR = value;
}
}
}
else {
/* RX is left channel mono */
while (dma_rec_data.size > 0) {
if (IIS_RX_FULL_COUNT < 2) {
return;
}
/* Discard every other sample since ADC clock is 1/2 LRCK */
value = IISFIFO_RD;
IISFIFO_RD;
value = (uint16_t)value | (value << 16);
*dma_rec_data.p++ = value;
dma_rec_data.size -= 4;
if (audio_output_source != AUDIO_SRC_PLAYBACK) {
if (IIS_TX_FREE_COUNT >= 16) {
/* Resync the output FIFO - it ran dry */
IISFIFO_WR = 0;
IISFIFO_WR = 0;
}
value = *((int32_t *)dma_rec_data.p - 1);
IISFIFO_WR = value;
IISFIFO_WR = value;
}
}
}
more_ready = pcm_callback_more_ready;
if (more_ready == NULL || more_ready(0) < 0) {
/* Finished recording */
pcm_rec_dma_stop();
pcm_rec_dma_stopped_callback();
}
}
#else
void fiq_record(void)
{
register pcm_more_callback_type2 more_ready;
while (dma_rec_data.size > 0) {
if (IIS_RX_FULL_COUNT < 2) {
return;
}
#if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
*dma_rec_data.p++ = IISFIFO_RDH;
*dma_rec_data.p++ = IISFIFO_RDH;
#elif TRANSFER_SIZE == 32
*dma_rec_data.p++ = IISFIFO_RD;
#endif
#elif SAMPLE_SIZE == 32
*dma_rec_data.p++ = IISFIFO_RD >> 16;
*dma_rec_data.p++ = IISFIFO_RD >> 16;
#endif
dma_rec_data.size -= 4;
}
more_ready = pcm_callback_more_ready;
if (more_ready == NULL || more_ready(0) < 0) {
/* Finished recording */
pcm_rec_dma_stop();
pcm_rec_dma_stopped_callback();
}
}
#endif /* SANSA_E200 */
/* Continue transferring data in */
void pcm_record_more(void *start, size_t size)
{
pcm_rec_peak_addr = start; /* Start peaking at dest */
dma_rec_data.p = start; /* Start of RX buffer */
dma_rec_data.size = size; /* Bytes to transfer */
}
void pcm_rec_dma_stop(void)
{
/* disable interrupt */
IIS_IRQRX_REG &= ~IIS_IRQRX;
dma_rec_data.state = 0;
dma_rec_data.size = 0;
#if NUM_CORES > 1
dma_rec_data.core = 0x00;
#endif
/* disable fifo */
IISCONFIG &= ~IIS_RXFIFOEN;
IISFIFO_CFG |= IIS_RXCLR;
}
void pcm_rec_dma_start(void *addr, size_t size)
{
pcm_rec_dma_stop();
pcm_rec_peak_addr = addr;
dma_rec_data.p = addr;
dma_rec_data.size = size;
#if NUM_CORES > 1
/* This will become more important later - and different ! */
dma_rec_data.core = processor_id(); /* save initiating core */
#endif
/* setup FIQ handler */
fiq_function = fiq_record;
/* interrupt on full fifo, enable record fifo interrupt */
dma_rec_data.state = 1;
/* enable RX FIFO */
IISCONFIG |= IIS_RXFIFOEN;
/* enable IIS interrupt as FIQ */
CPU_INT_PRIORITY |= IIS_MASK;
CPU_INT_EN = IIS_MASK;
}
void pcm_rec_dma_close(void)
{
pcm_rec_dma_stop();
} /* pcm_close_recording */
void pcm_rec_dma_init(void)
{
#if defined(IPOD_COLOR) || defined (IPOD_4G)
/* The usual magic from IPL - I'm guessing this configures the headphone
socket to be input or output - in this case, input. */
GPIOI_OUTPUT_VAL &= ~0x40;
GPIOA_OUTPUT_VAL &= ~0x4;
#endif
pcm_rec_dma_stop();
} /* pcm_init */
const void * pcm_rec_dma_get_peak_buffer(int *count)
{
unsigned long addr = (unsigned long)pcm_rec_peak_addr;
unsigned long end = (unsigned long)dma_rec_data.p;
*count = (end >> 2) - (addr >> 2);
return (void *)(addr & ~3);
} /* pcm_rec_dma_get_peak_buffer */
#endif /* HAVE_RECORDING */
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