617d1e9f6b
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30104 a1c6a512-1295-4272-9138-f99709370657
89 lines
3.5 KiB
C
89 lines
3.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef CLKCTRL_IMX233_H
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#define CLKCTRL_IMX233_H
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#include "config.h"
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#include "system.h"
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#include "cpu.h"
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#define HW_CLKCTRL_BASE 0x80040000
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#define HW_CLKCTRL_PLLCTRL0 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x0))
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#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BP 20
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#define HW_CLKCTRL_PLLCTRL0__DIV_SEL_BM (3 << 20)
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#define HW_CLKCTRL_PLLCTRL1 (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x10))
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#define HW_CLKCTRL_CPU (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x20))
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#define HW_CLKCTRL_CPU__DIV_CPU_BP 0
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#define HW_CLKCTRL_CPU__DIV_CPU_BM 0x3f
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#define HW_CLKCTRL_CPU__BUSY_REF_CPU (1 << 28)
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#define HW_CLKCTRL_HBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x30))
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#define HW_CLKCTRL_HBUS__DIV_BP 0
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#define HW_CLKCTRL_HBUS__DIV_BM 0x1f
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#define HW_CLKCTRL_XTAL (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x50))
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#define HW_CLKCTRL_XTAL__TIMROT_CLK32K_GATE (1 << 26)
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#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
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#define HW_CLKCTRL_PIX__DIV_BM 0xfff
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#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
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#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
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#define HW_CLKCTRL_CLKSEQ (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x110))
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#define HW_CLKCTRL_CLKSEQ__BYPASS_PIX (1 << 1)
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#define HW_CLKCTRL_CLKSEQ__BYPASS_SSP (1 << 5)
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#define HW_CLKCTRL_CLKSEQ__BYPASS_CPU (1 << 7)
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#define HW_CLKCTRL_FRAC (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xf0))
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#define HW_CLKCTRL_FRAC_CPU (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf0))
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#define HW_CLKCTRL_FRAC_EMI (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf1))
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#define HW_CLKCTRL_FRAC_PIX (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf2))
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#define HW_CLKCTRL_FRAC_IO (*(volatile uint8_t *)(HW_CLKCTRL_BASE + 0xf3))
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#define HW_CLKCTRL_FRAC_XX__XXDIV_BM 0x3f
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#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
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#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
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#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
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#define HW_CLKCTRL_RESET_CHIP 0x2
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#define HW_CLKCTRL_RESET_DIG 0x1
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enum imx233_clock_t
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{
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CLK_PIX, /* div, frac */
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CLK_SSP, /* div, frac */
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CLK_IO, /* div */
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CLK_CPU, /* div, frac */
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CLK_AHB /* div */
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};
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void imx233_enable_timrot_xtal_clk32k(bool enable);
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/* only use it for non-fractional clocks (ie not for IO) */
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void imx233_enable_clock(enum imx233_clock_t clk, bool enable);
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void imx233_set_clock_divisor(enum imx233_clock_t clk, int div);
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/* call with fracdiv=0 to disable it */
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void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv);
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void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass);
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#endif /* CLKCTRL_IMX233_H */
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