288 lines
8.7 KiB
C
288 lines
8.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "button.h"
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#include "system-target.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked, \
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weak, alias("fiq_dummy")));
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default_interrupt(INT_UART0);
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default_interrupt(INT_UART1);
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default_interrupt(INT_TIMER0);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_GPIO0);
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default_interrupt(INT_SW_INT0);
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default_interrupt(INT_AHB0_MAILBOX);
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default_interrupt(INT_RTC);
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default_interrupt(INT_SCU);
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default_interrupt(INT_SD);
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default_interrupt(INT_SPI);
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default_interrupt(INT_HDMA);
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default_interrupt(INT_A2A_BRIDGE);
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default_interrupt(INT_I2C);
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default_interrupt(INT_I2S);
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default_interrupt(INT_UDC);
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default_interrupt(INT_UHC);
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default_interrupt(INT_PWM0);
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default_interrupt(INT_PWM1);
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default_interrupt(INT_PWM2);
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default_interrupt(INT_PWM3);
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default_interrupt(INT_ADC);
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default_interrupt(INT_GPIO1);
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default_interrupt(INT_VIP);
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default_interrupt(INT_DWDMA);
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default_interrupt(INT_NANDC);
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default_interrupt(INT_LCDC);
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default_interrupt(INT_DSP);
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default_interrupt(INT_SW_INT1);
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default_interrupt(INT_SW_INT2);
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default_interrupt(INT_SW_INT3);
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static void (* const irqvector[])(void) USED_ATTR =
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{
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INT_UART0,INT_UART1,INT_TIMER0,INT_TIMER1,INT_TIMER2,INT_GPIO0,INT_SW_INT0,INT_AHB0_MAILBOX,
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INT_RTC,INT_SCU,INT_SD,INT_SPI,INT_HDMA,INT_A2A_BRIDGE,INT_I2C,INT_I2S,
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INT_UDC,INT_UHC,INT_PWM0,INT_PWM1,INT_PWM2,INT_PWM3,INT_ADC,INT_GPIO1,
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INT_VIP,INT_DWDMA,INT_NANDC,INT_LCDC,INT_DSP,INT_SW_INT1,INT_SW_INT2,INT_SW_INT3
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};
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static const char * const irqname[] =
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{
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"INT_UART0","INT_UART1","INT_TIMER0","INT_TIMER1","INT_TIMER2","INT_GPIO0","INT_SW_INT0","INT_AHB0_MAILBOX",
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"INT_RTC","INT_SCU","INT_SD","INT_SPI","INT_HDMA","INT_A2A_BRIDGE","INT_I2C","INT_I2S",
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"INT_UDC","INT_UHC","INT_PWM0","INT_PWM1","INT_PWM2","INT_PWM3","INT_ADC","INT_GPIO1",
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"INT_VIP","INT_DWDMA","INT_NANDC","INT_LCDC","INT_DSP","INT_SW_INT1","INT_SW_INT2","INT_SW_INT3"
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};
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static void UIRQ(void)
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{
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unsigned int offset = INTC_ISR & 0x1f;
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panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
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}
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void irq_handler(void)
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{
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asm volatile("stmfd sp!, {r0-r5, ip, lr} \n" /* store context */
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"ldr r4, =0x18080000 \n" /* INTC base */
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"ldr r5, [r4, #0x104] \n" /* INTC_ISR */
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"and r5, r5, #0x1f \n" /* irq_no = INTC_ISR & 0x1f */
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"ldr r3, =irqvector \n"
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"ldr r3,[r3, r5, lsl #2] \n"
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"blx r3 \n" /* irqvector[irq_no]() */
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"mov r3, #1 \n"
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"lsl r5, r3, r5 \n" /* clear interrupt */
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"str r5, [r4, #0x118] \n" /* INTC_ICCR = (1<<irq_no) */
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"ldmfd sp!, {r0-r5, ip, lr} \n" /* restore context */
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"subs pc, lr, #4 \n");
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}
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void fiq_dummy(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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void system_init(void)
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{
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/* disable WDT just in case nand loader activated it */
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WDTCON &= ~(1<<3);
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#ifndef BOOTLOADER
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/* SDRAM tweaks */
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MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */
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MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */
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MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */
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MCSDR_T_RP = 1; /* precharge period */
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MCSDR_T_RCD = 1; /* active to RD/WR delay */
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/* turn off clock for unused modules */
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SCU_CLKCFG |= CLKCFG_WDT | /* WDT pclk */
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CLKCFG_RTC | /* RTC pclk */
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CLKCFG_HSADC | /* HS_ADC clock */
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CLKCFG_HCLK_HSADC | /* HS_ADC HCLK */
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CLKCFG_SPI | /* SPI clock */
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CLKCFG_UART1 | /* UART1 clock */
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CLKCFG_UART0 | /* UART0 clock */
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CLKCFG_VIP | /* VIP clock */
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CLKCFG_HCLK_VIP | /* VIP HCLK */
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CLKCFG_LCDC | /* LCDC clock */
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CLKCFG_NAND | /* NAND HCLK */
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CLKCFG_UHC | /* USB host HCLK */
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CLKCFG_DSP | /* DSP clock */
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CLKCFG_OTP; /* OTP clock (dunno what it is */
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/* turn off DSP pll */
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SCU_PLLCON2 |= (1<<22);
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/* turn off codec pll */
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SCU_PLLCON3 |= (1<<22);
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#endif
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}
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/* not tested */
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void system_reboot(void)
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{
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/* use Watchdog to reset */
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SCU_CLKCFG &= ~CLKCFG_WDT;
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WDTLR = 1;
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WDTCON = (1<<4) | (1<<3);
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/* Wait for reboot to kick in */
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while(1);
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}
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void system_exception_wait(void)
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{
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/* wait until button release (if a button is pressed) */
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while(button_read_device());
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/* then wait until next button press */
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while(!button_read_device());
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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/* usecs may be at most 2^32/200 (~21 seconds) for 200MHz max cpu freq */
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void udelay(unsigned usecs)
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{
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unsigned cycles_per_usec;
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unsigned delay;
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if (cpu_frequency == CPUFREQ_MAX) {
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cycles_per_usec = (CPUFREQ_MAX + 999999) / 1000000;
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} else {
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cycles_per_usec = (CPUFREQ_NORMAL + 999999) / 1000000;
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}
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delay = (usecs * cycles_per_usec) / 5;
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asm volatile(
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"1: subs %0, %0, #1 \n" /* 1 cycle */
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" nop \n" /* 1 cycle */
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" bne 1b \n" /* 3 cycles */
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: : "r"(delay)
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);
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}
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static void cache_invalidate_way(int way)
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{
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/* Issue invalidata way command to the cache controler */
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CACHEOP = ((way<<31)|0x2);
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/* wait for invalidate process to complete */
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while (CACHEOP & 0x03);
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}
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void commit_discard_idcache(void)
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{
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int old_irq = disable_irq_save();
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cache_invalidate_way(0);
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cache_invalidate_way(1);
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restore_irq(old_irq);
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}
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void commit_discard_dcache (void) __attribute__((alias("commit_discard_idcache")));
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void commit_discard_dcache_range (const void *base, unsigned int size)
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{
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/* 0x01 is opcode for cache line commit discard */
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uint32_t end_opcode = (uint32_t)((uintptr_t)base + size) | 0x01;
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uint32_t opcode = (uint32_t)((uintptr_t)base & 0xffffffe0) | 0x01;
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while (opcode <= end_opcode)
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{
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while (CACHEOP & 0x03);
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CACHEOP = opcode;
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opcode += 32;
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}
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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static inline void set_sdram_timing(int ahb_freq)
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{
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MCSDR_T_REF = (125*ahb_freq/1000000) >> 3;
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MCSDR_T_RFC = (64*ahb_freq/1000000)/1000;
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}
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void set_cpu_frequency(long frequency)
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{
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if (cpu_frequency == frequency)
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return;
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set_sdram_timing(12000000);
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if (frequency == CPUFREQ_MAX)
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{
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/* PLL set to 200 Mhz
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* PLL:ARM = 1:1
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* ARM:AHB = 2:1
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* AHB:APB = 2:1
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*/
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SCU_DIVCON1 = (SCU_DIVCON1 &~ 0x1f) | (1<<3)|1;
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SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)); /*((24/6)*50)/1*/
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/* wait for PLL lock ~0.3 ms */
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while (!(SCU_STATUS & 1));
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/* leave SLOW mode */
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SCU_DIVCON1 &= ~1;
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set_sdram_timing(CPUFREQ_MAX/2);
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}
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else
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{
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/* PLL set to 100 MHz
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* PLL:ARM = 2:1
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* ARM:AHB = 1:1
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* AHB:APB = 1:1
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*/
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SCU_DIVCON1 = (SCU_DIVCON1 & ~0x1f) | (1<<2)|1;
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SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)|(1<<1)); /*((24/6)*50)/2*/
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/* wait for PLL lock ~0.3 ms */
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while (!(SCU_STATUS & 1));
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/* leave SLOW mode */
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SCU_DIVCON1 &= ~1;
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set_sdram_timing(CPUFREQ_NORMAL);
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}
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cpu_frequency = frequency;
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}
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#endif
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