c08ce1b829
Author: Lorenzo Miori Flyspray: FS#12348 git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31544 a1c6a512-1295-4272-9138-f99709370657
185 lines
3.4 KiB
C
185 lines
3.4 KiB
C
/* This file originates from the linux kernel provided in Samsung's YP-R0 Open
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* Source package (second release, which includes some driver modules sources).
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*/
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#ifndef __IOCTL_GPIO_H__
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#define __IOCTL_GPIO_H__
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#include <sys/ioctl.h>
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//#include "iomux.h"
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typedef struct {
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int num;
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int mode;
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int val;
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}__attribute__((packed)) R0GPIOInfo;
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#define IOCTL_GPIO_MAGIC 'G'
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#define E_IOCTL_GPIO_SET_MUX 0
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#define E_IOCTL_GPIO_UNSET_MUX 1
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#define E_IOCTL_GPIO_SET_TYPE 2
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#define E_IOCTL_GPIO_SET_OUTPUT 3
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#define E_IOCTL_GPIO_SET_INPUT 4
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#define E_IOCTL_GPIO_SET_HIGH 5
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#define E_IOCTL_GPIO_SET_LOW 6
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#define E_IOCTL_GPIO_GET_VAL 7
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#define E_IOCTL_GPIO_IS_HIGH 8
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#define E_IOCTL_GPIO_MAX_NR 9
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#define DEV_CTRL_GPIO_SET_MUX _IOW(IOCTL_GPIO_MAGIC, 0, R0GPIOInfo)
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#define DEV_CTRL_GPIO_UNSET_MUX _IOW(IOCTL_GPIO_MAGIC, 1, R0GPIOInfo)
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#define DEV_CTRL_GPIO_SET_TYPE _IOW(IOCTL_GPIO_MAGIC, 2, R0GPIOInfo)
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#define DEV_CTRL_GPIO_SET_OUTPUT _IOW(IOCTL_GPIO_MAGIC, 3, R0GPIOInfo)
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#define DEV_CTRL_GPIO_SET_INPUT _IOW(IOCTL_GPIO_MAGIC, 4, R0GPIOInfo)
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#define DEV_CTRL_GPIO_SET_HIGH _IOW(IOCTL_GPIO_MAGIC, 5, R0GPIOInfo)
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#define DEV_CTRL_GPIO_SET_LOW _IOW(IOCTL_GPIO_MAGIC, 6, R0GPIOInfo)
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#define DEV_CTRL_GPIO_GET_VAL _IOW(IOCTL_GPIO_MAGIC, 7, R0GPIOInfo)
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#define DEV_CTRL_GPIO_IS_HIGH _IOW(IOCTL_GPIO_MAGIC, 8, R0GPIOInfo)
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typedef enum
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{
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GPIO1_0 = 0, /* GPIO group 1 start */
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GPIO1_1,
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GPIO1_2,
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GPIO1_3,
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GPIO1_4,
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GPIO1_5,
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GPIO1_6,
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GPIO1_7,
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GPIO1_8,
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GPIO1_9,
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GPIO1_10,
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GPIO1_11,
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GPIO1_12,
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GPIO1_13,
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GPIO1_14,
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GPIO1_15,
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GPIO1_16,
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GPIO1_17,
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GPIO1_18,
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GPIO1_19,
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GPIO1_20,
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GPIO1_21,
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GPIO1_22,
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GPIO1_23,
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GPIO1_24,
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GPIO1_25,
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GPIO1_26,
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GPIO1_27,
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GPIO1_28,
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GPIO1_29,
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GPIO1_30,
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GPIO1_31,
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GPIO2_0, /* GPIO group 2 start */
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GPIO2_1,
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GPIO2_2,
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GPIO2_3,
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GPIO2_4,
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GPIO2_5,
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GPIO2_6,
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GPIO2_7,
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GPIO2_8,
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GPIO2_9,
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GPIO2_10,
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GPIO2_11,
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GPIO2_12,
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GPIO2_13,
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GPIO2_14,
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GPIO2_15,
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GPIO2_16,
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GPIO2_17,
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GPIO2_18,
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GPIO2_19,
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GPIO2_20,
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GPIO2_21,
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GPIO2_22,
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GPIO2_23,
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GPIO2_24,
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GPIO2_25,
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GPIO2_26,
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GPIO2_27,
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GPIO2_28,
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GPIO2_29,
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GPIO2_30,
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GPIO2_31,
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GPIO3_0, /* GPIO group 3 start */
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GPIO3_1,
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GPIO3_2,
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GPIO3_3,
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GPIO3_4,
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GPIO3_5,
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GPIO3_6,
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GPIO3_7,
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GPIO3_8,
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GPIO3_9,
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GPIO3_10,
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GPIO3_11,
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GPIO3_12,
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GPIO3_13,
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GPIO3_14,
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GPIO3_15,
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GPIO3_16,
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GPIO3_17,
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GPIO3_18,
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GPIO3_19,
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GPIO3_20,
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GPIO3_21,
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GPIO3_22,
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GPIO3_23,
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GPIO3_24,
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GPIO3_25,
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GPIO3_26,
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GPIO3_27,
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GPIO3_28,
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GPIO3_29,
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GPIO3_30,
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GPIO3_31,
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}R0_MX37_GPIO;
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typedef enum
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{
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CONFIG_ALT0,
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CONFIG_ALT1,
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CONFIG_ALT2,
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CONFIG_ALT3,
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CONFIG_ALT4,
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CONFIG_ALT5,
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CONFIG_ALT6,
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CONFIG_ALT7,
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CONFIG_GPIO,
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CONFIG_SION = 0x01 << 4,
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CONFIG_DEFAULT
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} R0_MX37_PIN_CONFIG;
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#ifndef __MACH_MX37_IOMUX_H__
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typedef enum
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{
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PAD_CTL_SRE_SLOW = 0x0 << 0,
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PAD_CTL_SRE_FAST = 0x1 << 0,
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PAD_CTL_DRV_LOW = 0x0 << 1,
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PAD_CTL_DRV_MEDIUM = 0x1 << 1,
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PAD_CTL_DRV_HIGH = 0x2 << 1,
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PAD_CTL_DRV_MAX = 0x3 << 1,
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PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
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PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
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PAD_CTL_100K_PD = 0x0 << 4,
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PAD_CTL_47K_PU = 0x1 << 4,
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PAD_CTL_100K_PU = 0x2 << 4,
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PAD_CTL_22K_PU = 0x3 << 4,
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PAD_CTL_PUE_KEEPER = 0x0 << 6,
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PAD_CTL_PUE_PULL = 0x1 << 6,
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PAD_CTL_PKE_NONE = 0x0 << 7,
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PAD_CTL_PKE_ENABLE = 0x1 << 7,
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PAD_CTL_HYS_NONE = 0x0 << 8,
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PAD_CTL_HYS_ENABLE = 0x1 << 8,
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PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
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PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
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PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
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PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
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} R0_MX37_PAD_CONFIG;
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#endif
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#endif /* __IOCTL_GPIO__H__ */
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