789df17dd9
The origin of the register value was never
moved in the desired register state due to a typo ('rhs' vs. 'rhd').
While looking at the code, I noticed the action taken
for the register value is another copy'n'paste error
from the ADD opcode above -> it added to the register value
instead of MOVing the current value.
Patch submitted upstream.
cppcheck reported:
[lib/unwarminder/unwarm_thumb.c:473]: (warning) Redundant assignment of 'state.regData[rhd].o' to itself.
Change-Id: I78cdbf37a191007a3bddbaa350b906dbce2fe671
740 lines
25 KiB
C
740 lines
25 KiB
C
/***************************************************************************
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* ARM Stack Unwinder, Michael.McTernan.2001@cs.bris.ac.uk
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*
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* This program is PUBLIC DOMAIN.
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* This means that there is no copyright and anyone is able to take a copy
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* for free and use it as they wish, with or without modifications, and in
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* any context, commercially or otherwise. The only limitation is that I
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* don't guarantee that the software is fit for any purpose or accept any
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* liability for it's use or misuse - this software is without warranty.
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***************************************************************************
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* File Description: Abstract interpretation for Thumb mode.
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**************************************************************************/
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#define MODULE_NAME "UNWARM_THUMB"
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/***************************************************************************
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* Include Files
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**************************************************************************/
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#include "types.h"
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#if defined(UPGRADE_ARM_STACK_UNWIND)
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#include <stdio.h>
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#include "unwarm.h"
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/***************************************************************************
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* Manifest Constants
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**************************************************************************/
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/***************************************************************************
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* Type Definitions
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**************************************************************************/
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/***************************************************************************
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* Variables
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**************************************************************************/
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/***************************************************************************
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* Macros
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**************************************************************************/
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/***************************************************************************
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* Local Functions
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**************************************************************************/
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/** Sign extend an 11 bit value.
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* This function simply inspects bit 11 of the input \a value, and if
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* set, the top 5 bits are set to give a 2's compliment signed value.
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* \param value The value to sign extend.
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* \return The signed-11 bit value stored in a 16bit data type.
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*/
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static SignedInt16 signExtend11(Int16 value)
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{
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if(value & 0x400)
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{
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value |= 0xf800;
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}
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return value;
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}
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/***************************************************************************
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* Global Functions
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**************************************************************************/
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UnwResult UnwStartThumb(UnwState * const state)
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{
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Boolean found = FALSE;
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Int16 t = UNW_MAX_INSTR_COUNT;
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do
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{
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Int16 instr;
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/* Attempt to read the instruction */
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if(!state->cb->readH(state->regData[15].v & (~0x1), &instr))
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{
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return UNWIND_IREAD_H_FAIL;
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}
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UnwPrintd4("T %x %x %04x:",
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state->regData[13].v, state->regData[15].v, instr);
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/* Check that the PC is still on Thumb alignment */
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if(!(state->regData[15].v & 0x1))
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{
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UnwPrintd1("\nError: PC misalignment\n");
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return UNWIND_INCONSISTENT;
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}
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/* Check that the SP and PC have not been invalidated */
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if(!M_IsOriginValid(state->regData[13].o) || !M_IsOriginValid(state->regData[15].o))
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{
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UnwPrintd1("\nError: PC or SP invalidated\n");
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return UNWIND_INCONSISTENT;
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}
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/* Format 1: Move shifted register
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* LSL Rd, Rs, #Offset5
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* LSR Rd, Rs, #Offset5
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* ASR Rd, Rs, #Offset5
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*/
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if((instr & 0xe000) == 0x0000 && (instr & 0x1800) != 0x1800)
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{
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Boolean signExtend;
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Int8 op = (instr & 0x1800) >> 11;
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Int8 offset5 = (instr & 0x07c0) >> 6;
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Int8 rs = (instr & 0x0038) >> 3;
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Int8 rd = (instr & 0x0007);
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switch(op)
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{
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case 0: /* LSL */
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UnwPrintd6("LSL r%d, r%d, #%d\t; r%d %s", rd, rs, offset5, rs, M_Origin2Str(state->regData[rs].o));
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state->regData[rd].v = state->regData[rs].v << offset5;
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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case 1: /* LSR */
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UnwPrintd6("LSR r%d, r%d, #%d\t; r%d %s", rd, rs, offset5, rs, M_Origin2Str(state->regData[rs].o));
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state->regData[rd].v = state->regData[rs].v >> offset5;
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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case 2: /* ASR */
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UnwPrintd6("ASL r%d, r%d, #%d\t; r%d %s", rd, rs, offset5, rs, M_Origin2Str(state->regData[rs].o));
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signExtend = (state->regData[rs].v & 0x8000) ? TRUE : FALSE;
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state->regData[rd].v = state->regData[rs].v >> offset5;
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if(signExtend)
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{
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state->regData[rd].v |= 0xffffffff << (32 - offset5);
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}
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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}
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}
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/* Format 2: add/subtract
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* ADD Rd, Rs, Rn
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* ADD Rd, Rs, #Offset3
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* SUB Rd, Rs, Rn
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* SUB Rd, Rs, #Offset3
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*/
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else if((instr & 0xf800) == 0x1800)
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{
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Boolean I = (instr & 0x0400) ? TRUE : FALSE;
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Boolean op = (instr & 0x0200) ? TRUE : FALSE;
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Int8 rn = (instr & 0x01c0) >> 6;
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Int8 rs = (instr & 0x0038) >> 3;
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Int8 rd = (instr & 0x0007);
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/* Print decoding */
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UnwPrintd6("%s r%d, r%d, %c%d\t;",
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op ? "SUB" : "ADD",
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rd, rs,
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I ? '#' : 'r',
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rn);
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UnwPrintd5("r%d %s, r%d %s",
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rd, M_Origin2Str(state->regData[rd].o),
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rs, M_Origin2Str(state->regData[rs].o));
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if(!I)
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{
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UnwPrintd3(", r%d %s", rn, M_Origin2Str(state->regData[rn].o));
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/* Perform calculation */
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if(op)
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{
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state->regData[rd].v = state->regData[rs].v - state->regData[rn].v;
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}
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else
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{
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state->regData[rd].v = state->regData[rs].v + state->regData[rn].v;
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}
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/* Propagate the origin */
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if(M_IsOriginValid(state->regData[rs].v) &&
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M_IsOriginValid(state->regData[rn].v))
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{
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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}
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else
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{
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state->regData[rd].o = REG_VAL_INVALID;
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}
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}
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else
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{
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/* Perform calculation */
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if(op)
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{
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state->regData[rd].v = state->regData[rs].v - rn;
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}
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else
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{
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state->regData[rd].v = state->regData[rs].v + rn;
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}
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/* Propagate the origin */
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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}
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}
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/* Format 3: move/compare/add/subtract immediate
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* MOV Rd, #Offset8
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* CMP Rd, #Offset8
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* ADD Rd, #Offset8
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* SUB Rd, #Offset8
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*/
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else if((instr & 0xe000) == 0x2000)
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{
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Int8 op = (instr & 0x1800) >> 11;
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Int8 rd = (instr & 0x0700) >> 8;
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Int8 offset8 = (instr & 0x00ff);
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switch(op)
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{
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case 0: /* MOV */
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UnwPrintd3("MOV r%d, #0x%x", rd, offset8);
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state->regData[rd].v = offset8;
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state->regData[rd].o = REG_VAL_FROM_CONST;
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break;
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case 1: /* CMP */
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/* Irrelevant to unwinding */
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UnwPrintd1("CMP ???");
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break;
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case 2: /* ADD */
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UnwPrintd5("ADD r%d, #0x%x\t; r%d %s",
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rd, offset8, rd, M_Origin2Str(state->regData[rd].o));
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state->regData[rd].v += offset8;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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case 3: /* SUB */
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UnwPrintd5("SUB r%d, #0x%d\t; r%d %s",
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rd, offset8, rd, M_Origin2Str(state->regData[rd].o));
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state->regData[rd].v -= offset8;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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}
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}
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/* Format 4: ALU operations
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* AND Rd, Rs
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* EOR Rd, Rs
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* LSL Rd, Rs
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* LSR Rd, Rs
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* ASR Rd, Rs
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* ADC Rd, Rs
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* SBC Rd, Rs
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* ROR Rd, Rs
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* TST Rd, Rs
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* NEG Rd, Rs
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* CMP Rd, Rs
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* CMN Rd, Rs
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* ORR Rd, Rs
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* MUL Rd, Rs
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* BIC Rd, Rs
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* MVN Rd, Rs
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*/
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else if((instr & 0xfc00) == 0x4000)
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{
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Int8 op = (instr & 0x03c0) >> 6;
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Int8 rs = (instr & 0x0038) >> 3;
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Int8 rd = (instr & 0x0007);
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#if defined(UNW_DEBUG)
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static const char * const mnu[16] =
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{ "AND", "EOR", "LSL", "LSR",
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"ASR", "ADC", "SBC", "ROR",
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"TST", "NEG", "CMP", "CMN",
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"ORR", "MUL", "BIC", "MVN" };
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#endif
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/* Print the mnemonic and registers */
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switch(op)
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{
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case 0: /* AND */
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case 1: /* EOR */
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case 2: /* LSL */
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case 3: /* LSR */
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case 4: /* ASR */
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case 7: /* ROR */
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case 9: /* NEG */
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case 12: /* ORR */
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case 13: /* MUL */
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case 15: /* MVN */
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UnwPrintd8("%s r%d ,r%d\t; r%d %s, r%d %s",
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mnu[op],
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rd, rs,
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rd, M_Origin2Str(state->regData[rd].o),
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rs, M_Origin2Str(state->regData[rs].o));
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break;
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case 5: /* ADC */
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case 6: /* SBC */
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UnwPrintd4("%s r%d, r%d", mnu[op], rd, rs);
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break;
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case 8: /* TST */
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case 10: /* CMP */
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case 11: /* CMN */
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/* Irrelevant to unwinding */
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UnwPrintd2("%s ???", mnu[op]);
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break;
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case 14: /* BIC */
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UnwPrintd5("r%d ,r%d\t; r%d %s",
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rd, rs,
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rs, M_Origin2Str(state->regData[rs].o));
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state->regData[rd].v &= !state->regData[rs].v;
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break;
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}
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/* Perform operation */
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switch(op)
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{
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case 0: /* AND */
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state->regData[rd].v &= state->regData[rs].v;
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break;
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case 1: /* EOR */
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state->regData[rd].v ^= state->regData[rs].v;
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break;
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case 2: /* LSL */
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state->regData[rd].v <<= state->regData[rs].v;
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break;
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case 3: /* LSR */
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state->regData[rd].v >>= state->regData[rs].v;
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break;
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case 4: /* ASR */
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if(state->regData[rd].v & 0x80000000)
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{
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state->regData[rd].v >>= state->regData[rs].v;
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state->regData[rd].v |= 0xffffffff << (32 - state->regData[rs].v);
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}
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else
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{
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state->regData[rd].v >>= state->regData[rs].v;
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}
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break;
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case 5: /* ADC */
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case 6: /* SBC */
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case 8: /* TST */
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case 10: /* CMP */
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case 11: /* CMN */
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break;
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case 7: /* ROR */
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state->regData[rd].v = (state->regData[rd].v >> state->regData[rs].v) |
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(state->regData[rd].v << (32 - state->regData[rs].v));
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break;
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case 9: /* NEG */
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state->regData[rd].v = -state->regData[rs].v;
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break;
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case 12: /* ORR */
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state->regData[rd].v |= state->regData[rs].v;
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break;
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case 13: /* MUL */
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state->regData[rd].v *= state->regData[rs].v;
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break;
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case 14: /* BIC */
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state->regData[rd].v &= !state->regData[rs].v;
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break;
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case 15: /* MVN */
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state->regData[rd].v = !state->regData[rs].v;
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break;
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}
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/* Propagate data origins */
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switch(op)
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{
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case 0: /* AND */
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case 1: /* EOR */
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case 2: /* LSL */
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case 3: /* LSR */
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case 4: /* ASR */
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case 7: /* ROR */
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case 12: /* ORR */
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case 13: /* MUL */
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case 14: /* BIC */
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if(M_IsOriginValid(state->regData[rd].o) && M_IsOriginValid(state->regData[rs].o))
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{
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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}
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else
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{
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state->regData[rd].o = REG_VAL_INVALID;
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}
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break;
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case 5: /* ADC */
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case 6: /* SBC */
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/* C-bit not tracked */
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state->regData[rd].o = REG_VAL_INVALID;
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break;
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case 8: /* TST */
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case 10: /* CMP */
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case 11: /* CMN */
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/* Nothing propagated */
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break;
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case 9: /* NEG */
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case 15: /* MVN */
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state->regData[rd].o = state->regData[rs].o;
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state->regData[rd].o |= REG_VAL_ARITHMETIC;
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break;
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}
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}
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/* Format 5: Hi register operations/branch exchange
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* ADD Rd, Hs
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* ADD Hd, Rs
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* ADD Hd, Hs
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*/
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else if((instr & 0xfc00) == 0x4400)
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{
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Int8 op = (instr & 0x0300) >> 8;
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Boolean h1 = (instr & 0x0080) ? TRUE: FALSE;
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Boolean h2 = (instr & 0x0040) ? TRUE: FALSE;
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Int8 rhs = (instr & 0x0038) >> 3;
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Int8 rhd = (instr & 0x0007);
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/* Adjust the register numbers */
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if(h2) rhs += 8;
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if(h1) rhd += 8;
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if(op != 3 && !h1 && !h2)
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{
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UnwPrintd1("\nError: h1 or h2 must be set for ADD, CMP or MOV\n");
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return UNWIND_ILLEGAL_INSTR;
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}
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switch(op)
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{
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case 0: /* ADD */
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UnwPrintd5("ADD r%d, r%d\t; r%d %s",
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rhd, rhs, rhs, M_Origin2Str(state->regData[rhs].o));
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state->regData[rhd].v += state->regData[rhs].v;
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state->regData[rhd].o = state->regData[rhs].o;
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state->regData[rhd].o |= REG_VAL_ARITHMETIC;
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break;
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case 1: /* CMP */
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/* Irrelevant to unwinding */
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UnwPrintd1("CMP ???");
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break;
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case 2: /* MOV */
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UnwPrintd5("MOV r%d, r%d\t; r%d %s",
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rhd, rhs, rhd, M_Origin2Str(state->regData[rhs].o));
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state->regData[rhd].v = state->regData[rhs].v;
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state->regData[rhd].o = state->regData[rhs].o;
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break;
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case 3: /* BX */
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UnwPrintd4("BX r%d\t; r%d %s\n",
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rhs, rhs, M_Origin2Str(state->regData[rhs].o));
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/* Only follow BX if the data was from the stack */
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if(state->regData[rhs].o == REG_VAL_FROM_STACK)
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{
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UnwPrintd2(" Return PC=0x%x\n", state->regData[rhs].v & (~0x1));
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/* Report the return address, including mode bit */
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if(!UnwReportRetAddr(state, state->regData[rhs].v))
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{
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return UNWIND_TRUNCATED;
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}
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/* Update the PC */
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state->regData[15].v = state->regData[rhs].v;
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/* Determine the new mode */
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if(state->regData[rhs].v & 0x1)
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{
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/* Branching to THUMB */
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/* Account for the auto-increment which isn't needed */
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state->regData[15].v -= 2;
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}
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else
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{
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/* Branch to ARM */
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return UnwStartArm(state);
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}
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}
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else
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{
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|
UnwPrintd4("\nError: BX to invalid register: r%d = 0x%x (%s)\n",
|
|
rhs, state->regData[rhs].o, M_Origin2Str(state->regData[rhs].o));
|
|
return UNWIND_FAILURE;
|
|
}
|
|
}
|
|
}
|
|
/* Format 9: PC-relative load
|
|
* LDR Rd,[PC, #imm]
|
|
*/
|
|
else if((instr & 0xf800) == 0x4800)
|
|
{
|
|
Int8 rd = (instr & 0x0700) >> 8;
|
|
Int8 word8 = (instr & 0x00ff);
|
|
Int32 address;
|
|
|
|
/* Compute load address, adding a word to account for prefetch */
|
|
address = (state->regData[15].v & (~0x3)) + 4 + (word8 << 2);
|
|
|
|
UnwPrintd3("LDR r%d, 0x%08x", rd, address);
|
|
|
|
if(!UnwMemReadRegister(state, address, &state->regData[rd]))
|
|
{
|
|
return UNWIND_DREAD_W_FAIL;
|
|
}
|
|
}
|
|
/* Format 13: add offset to Stack Pointer
|
|
* ADD sp,#+imm
|
|
* ADD sp,#-imm
|
|
*/
|
|
else if((instr & 0xff00) == 0xB000)
|
|
{
|
|
Int8 value = (instr & 0x7f) * 4;
|
|
|
|
/* Check the negative bit */
|
|
if((instr & 0x80) != 0)
|
|
{
|
|
UnwPrintd2("SUB sp,#0x%x", value);
|
|
state->regData[13].v -= value;
|
|
}
|
|
else
|
|
{
|
|
UnwPrintd2("ADD sp,#0x%x", value);
|
|
state->regData[13].v += value;
|
|
}
|
|
}
|
|
/* Format 14: push/pop registers
|
|
* PUSH {Rlist}
|
|
* PUSH {Rlist, LR}
|
|
* POP {Rlist}
|
|
* POP {Rlist, PC}
|
|
*/
|
|
else if((instr & 0xf600) == 0xb400)
|
|
{
|
|
Boolean L = (instr & 0x0800) ? TRUE : FALSE;
|
|
Boolean R = (instr & 0x0100) ? TRUE : FALSE;
|
|
Int8 rList = (instr & 0x00ff);
|
|
|
|
if(L)
|
|
{
|
|
Int8 r;
|
|
|
|
/* Load from memory: POP */
|
|
UnwPrintd2("POP {Rlist%s}\n", R ? ", PC" : "");
|
|
|
|
for(r = 0; r < 8; r++)
|
|
{
|
|
if(rList & (0x1 << r))
|
|
{
|
|
/* Read the word */
|
|
if(!UnwMemReadRegister(state, state->regData[13].v, &state->regData[r]))
|
|
{
|
|
return UNWIND_DREAD_W_FAIL;
|
|
}
|
|
|
|
/* Alter the origin to be from the stack if it was valid */
|
|
if(M_IsOriginValid(state->regData[r].o))
|
|
{
|
|
state->regData[r].o = REG_VAL_FROM_STACK;
|
|
}
|
|
|
|
state->regData[13].v += 4;
|
|
|
|
UnwPrintd3(" r%d = 0x%08x\n", r, state->regData[r].v);
|
|
}
|
|
}
|
|
|
|
/* Check if the PC is to be popped */
|
|
if(R)
|
|
{
|
|
/* Get the return address */
|
|
if(!UnwMemReadRegister(state, state->regData[13].v, &state->regData[15]))
|
|
{
|
|
return UNWIND_DREAD_W_FAIL;
|
|
}
|
|
|
|
/* Alter the origin to be from the stack if it was valid */
|
|
if(!M_IsOriginValid(state->regData[15].o))
|
|
{
|
|
/* Return address is not valid */
|
|
UnwPrintd1("PC popped with invalid address\n");
|
|
return UNWIND_FAILURE;
|
|
}
|
|
else
|
|
{
|
|
/* The bottom bit should have been set to indicate that
|
|
* the caller was from Thumb. This would allow return
|
|
* by BX for interworking APCS.
|
|
*/
|
|
if((state->regData[15].v & 0x1) == 0)
|
|
{
|
|
UnwPrintd2("Warning: Return address not to Thumb: 0x%08x\n",
|
|
state->regData[15].v);
|
|
|
|
/* Pop into the PC will not switch mode */
|
|
return UNWIND_INCONSISTENT;
|
|
}
|
|
|
|
/* Store the return address */
|
|
if(!UnwReportRetAddr(state, state->regData[15].v))
|
|
{
|
|
return UNWIND_TRUNCATED;
|
|
}
|
|
|
|
/* Now have the return address */
|
|
UnwPrintd2(" Return PC=%x\n", state->regData[15].v);
|
|
|
|
/* Update the pc */
|
|
state->regData[13].v += 4;
|
|
|
|
/* Compensate for the auto-increment, which isn't needed here */
|
|
state->regData[15].v -= 2;
|
|
}
|
|
}
|
|
|
|
}
|
|
else
|
|
{
|
|
SignedInt8 r;
|
|
|
|
/* Store to memory: PUSH */
|
|
UnwPrintd2("PUSH {Rlist%s}", R ? ", LR" : "");
|
|
|
|
/* Check if the LR is to be pushed */
|
|
if(R)
|
|
{
|
|
UnwPrintd3("\n lr = 0x%08x\t; %s",
|
|
state->regData[14].v, M_Origin2Str(state->regData[14].o));
|
|
|
|
state->regData[13].v -= 4;
|
|
|
|
/* Write the register value to memory */
|
|
if(!UnwMemWriteRegister(state, state->regData[13].v, &state->regData[14]))
|
|
{
|
|
return UNWIND_DWRITE_W_FAIL;
|
|
}
|
|
}
|
|
|
|
for(r = 7; r >= 0; r--)
|
|
{
|
|
if(rList & (0x1 << r))
|
|
{
|
|
UnwPrintd4("\n r%d = 0x%08x\t; %s",
|
|
r, state->regData[r].v, M_Origin2Str(state->regData[r].o));
|
|
|
|
state->regData[13].v -= 4;
|
|
|
|
if(!UnwMemWriteRegister(state, state->regData[13].v, &state->regData[r]))
|
|
{
|
|
return UNWIND_DWRITE_W_FAIL;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Format 18: unconditional branch
|
|
* B label
|
|
*/
|
|
else if((instr & 0xf800) == 0xe000)
|
|
{
|
|
SignedInt16 branchValue = signExtend11(instr & 0x07ff);
|
|
|
|
/* Branch distance is twice that specified in the instruction. */
|
|
branchValue *= 2;
|
|
|
|
UnwPrintd2("B %d \n", branchValue);
|
|
|
|
/* Update PC */
|
|
state->regData[15].v += branchValue;
|
|
|
|
/* Need to advance by a word to account for pre-fetch.
|
|
* Advance by a half word here, allowing the normal address
|
|
* advance to account for the other half word.
|
|
*/
|
|
state->regData[15].v += 2;
|
|
|
|
/* Display PC of next instruction */
|
|
UnwPrintd2(" New PC=%x", state->regData[15].v + 2);
|
|
|
|
}
|
|
else
|
|
{
|
|
UnwPrintd1("????");
|
|
|
|
/* Unknown/undecoded. May alter some register, so invalidate file */
|
|
UnwInvalidateRegisterFile(state->regData);
|
|
}
|
|
|
|
UnwPrintd1("\n");
|
|
|
|
/* Should never hit the reset vector */
|
|
if(state->regData[15].v == 0) return UNWIND_RESET;
|
|
|
|
/* Check next address */
|
|
state->regData[15].v += 2;
|
|
|
|
/* Garbage collect the memory hash (used only for the stack) */
|
|
UnwMemHashGC(state);
|
|
|
|
t--;
|
|
if(t == 0) return UNWIND_EXHAUSTED;
|
|
|
|
}
|
|
while(!found);
|
|
|
|
return UNWIND_SUCCESS;
|
|
}
|
|
|
|
#endif /* UPGRADE_ARM_STACK_UNWIND */
|
|
|
|
/* END OF FILE */
|
|
|