2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
136 lines
6.1 KiB
C
136 lines
6.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 Jens Arnold
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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unsigned isp1362_read_hc_reg16(unsigned reg);
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unsigned isp1362_read_hc_reg32(unsigned reg);
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void isp1362_write_hc_reg16(unsigned reg, unsigned data);
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void isp1362_write_hc_reg32(unsigned reg, unsigned data);
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#define ISP1362_OTG_CONTROL 0x62
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#define ISP1362_OTG_STATUS 0x67 /* read only */
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#define ISP1362_OTG_INTERRUPT 0x68
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#define ISP1362_OTG_INT_ENABLE 0x69
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#define ISP1362_OTG_TIMER 0x6a
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#define ISP1362_OTG_ALT_TIMER 0x6c
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#define ISP1362_HC_REVISION 0x00 /* read only */
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#define ISP1362_HC_CONTROL 0x01
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#define ISP1362_HC_COMMAND_STATUS 0x02
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#define ISP1362_HC_INT_STATUS 0x03
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#define ISP1362_HC_INT_ENABLE 0x04
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#define ISP1362_HC_INT_DISABLE 0x05
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#define ISP1362_HC_FM_INTERVAL 0x0d
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#define ISP1362_HC_FM_REMAINING 0x0e
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#define ISP1362_HC_FM_NUMBER 0x0f
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#define ISP1362_HC_LS_THRESHOLD 0x11
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#define ISP1362_HC_RH_DESCRIPTOR_A 0x12
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#define ISP1362_HC_RH_DESCRIPTOR_B 0x13
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#define ISP1362_HC_RH_STATUS 0x14
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#define ISP1362_HC_RH_PORT_STATUS1 0x15
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#define ISP1362_HC_RH_PORT_STATUS2 0x16
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#define ISP1362_HC_HARDWARE_CONFIG 0x20
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#define ISP1362_HC_DMA_CONFIG 0x21
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#define ISP1362_HC_TRANSFER_COUNTER 0x22
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#define ISP1362_HC_UP_INTERRUPT 0x24
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#define ISP1362_HC_UP_INT_ENABLE 0x25
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#define ISP1362_HC_CHIP_ID 0x27 /* read only */
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#define ISP1362_HC_SCRATCH 0x28
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#define ISP1362_HC_SOFTWARE_RESET 0x29 /* write only */
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#define ISP1362_HC_BUFFER_STATUS 0x2c
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#define ISP1362_HC_DIRECT_ADDR_LEN 0x32
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#define ISP1362_HC_DIRECT_ADDR_DATA 0x45
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#define ISP1362_HC_ISTL_BUF_SIZE 0x30
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#define ISP1362_HC_ISTL0_BUF_PORT 0x40
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#define ISP1362_HC_ISTL1_BUF_PORT 0x42
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#define ISP1362_HC_ISTL_TOGGLE_RATE 0x47
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#define ISP1362_HC_INTL_BUF_SIZE 0x33
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#define ISP1362_HC_INTL_BUF_PORT 0x43
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#define ISP1362_HC_INTL_BLK_SIZE 0x53
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#define ISP1362_HC_INTL_PRD_DONE_MAP 0x17 /* read only */
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#define ISP1362_HC_INTL_PTD_SKIP_MAP 0x18
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#define ISP1362_HC_INTL_LAST_PTD 0x19
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#define ISP1362_HC_INTL_CUR_ACT_PTD 0x1a /* read only */
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#define ISP1362_HC_ATL_BUF_SIZE 0x34
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#define ISP1362_HC_ATL_BUF_PORT 0x44
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#define ISP1362_HC_ATL_BLK_SIZE 0x54
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#define ISP1362_HC_ATL_PTD_DONE_MAP 0x1b /* read only */
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#define ISP1362_HC_ATL_PTD_SKIP_MAP 0x1c
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#define ISP1362_HC_ATL_LAST_PTD 0x1d
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#define ISP1362_HC_ATL_CUR_ACT_PTD 0x1e /* read only */
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#define ISP1362_HC_ATL_PTD_DONE_THR_CNT 0x51
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#define ISP1362_HC_ATL_PTD_DONE_THR_TMO 0x52
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unsigned isp1362_read_dc_reg16(unsigned reg);
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unsigned isp1362_read_dc_reg32(unsigned reg);
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void isp1362_write_dc_reg16(unsigned reg, unsigned data);
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void isp1362_write_dc_reg32(unsigned reg, unsigned data);
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#define ISP1362_DC_CTRL_OUT_CFG_W 0x20
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#define ISP1362_DC_CTRL_IN_CFG_W 0x21
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#define ISP1362_DC_ENDPOINT_CFG_BASE_W 0x22
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#define ISP1362_DC_CTRL_OUT_CFG_R 0x30
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#define ISP1362_DC_CTRL_IN_CFG_R 0x31
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#define ISP1362_DC_ENDPOINT_CFG_BASE_R 0x32
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#define ISP1362_DC_ADDRESS_W 0xb6
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#define ISP1362_DC_ADDRESS_R 0xb7
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#define ISP1362_DC_MODE_W 0xb8
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#define ISP1362_DC_MODE_R 0xb9
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#define ISP1362_DC_HARDWARE_CONFIG_W 0xba
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#define ISP1362_DC_HARDWARE_CONFIG_R 0xbb
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#define ISP1362_DC_INT_ENABLE_W 0xc2
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#define ISP1362_DC_INT_ENABLE_R 0xc3
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#define ISP1362_DC_DMA_CONFIG_W 0xf0
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#define ISP1362_DC_DMA_CONFIG_R 0xf1
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#define ISP1362_DC_DMA_COUNTER_W 0xf2
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#define ISP1362_DC_DMA_COUNTER_R 0xf3
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#define ISP1362_DC_RESET 0xf6
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#define ISP1362_DC_CTRL_IN_BUF_W 0x01
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#define ISP1362_DC_ENDPOINT_BUF_BASE_W 0x02
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#define ISP1362_DC_CTRL_OUT_BUF_R 0x10
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#define ISP1362_DC_ENDPOINT_BUF_BASE_R 0x12
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#define ISP1362_DC_CTRL_OUT_STALL 0x40
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#define ISP1362_DC_CTRL_IN_STALL 0x41
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#define ISP1362_DC_ENDPOINT_STALL_BASE 0x42
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#define ISP1362_DC_CTRL_OUT_STATUS_R 0x50
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#define ISP1362_DC_CTRL_IN_STATUS_R 0x51
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#define ISP1362_DC_ENDPOINT_STATUS_BASE_R 0x52
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#define ISP1362_DC_CTRL_IN_VALIDATE 0x61
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#define ISP1362_DC_ENDPOINT_VALIDATE_BASE 0x62
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#define ISP1362_DC_CTRL_OUT_CLEAR 0x70
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#define ISP1362_DC_ENDPOINT_CLEAR_BASE 0x72
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#define ISP1362_DC_CTRL_OUT_UNSTALL 0x80
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#define ISP1362_DC_CTRL_IN_UNSTALL 0x81
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#define ISP1362_DC_ENDPOINT_UNSTALL_BASE 0x82
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#define ISP1362_DC_CTRL_OUT_STAT_IMG_R 0xd0
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#define ISP1362_DC_CTRL_IN_STAT_IMG_R 0xd1
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#define ISP1362_DC_ENDPOINT_STAT_IMG_BASE_R 0xd2
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#define ISP1362_DC_SETUP_ACK 0xf4
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#define ISP1362_DC_CTRL_OUT_ERROR_R 0xa0
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#define ISP1362_DC_CTRL_IN_ERROR_R 0xa1
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#define ISP1362_DC_ENDPOINT_ERROR_BASE_R 0xa2
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#define ISP1362_DC_UNLOCK_DEVICE 0xb0
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#define ISP1362_DC_SCRATCH_W 0xb2
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#define ISP1362_DC_SCRATCH_R 0xb3
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#define ISP1362_DC_FRAME_NUMBER_R 0xb4
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#define ISP1362_DC_CHIP_ID_R 0xb5
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#define ISP1362_DC_INTERRUPT_R 0xc0
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void isp1362_init(void);
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