931 lines
25 KiB
C
931 lines
25 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "panic.h"
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#include "led.h"
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#include "msc-x1000.h"
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#include "gpio-x1000.h"
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#include "irq-x1000.h"
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#include "clk-x1000.h"
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#include "x1000/msc.h"
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#include "x1000/cpm.h"
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#include <string.h>
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#include <stddef.h>
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/* #define LOGF_ENABLE */
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#include "logf.h"
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/* TODO - this needs some auditing to better handle errors
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*
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* There should be a clearer code path involving errors. Especially we should
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* ensure that removing the card always resets the driver to a sane state.
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*/
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#define DEBOUNCE_TIME (HZ/10)
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static const msc_config msc_configs[] = {
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#if defined(FIIO_M3K)
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#define MSC_CLOCK_SOURCE X1000_CLK_SCLK_A
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{
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.msc_nr = 0,
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.msc_type = MSC_TYPE_SD,
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.bus_width = 4,
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.label = "microSD",
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.cd_gpio = GPIO_MSC0_CD,
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.cd_active_level = 0,
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},
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#elif defined(SHANLING_Q1)
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#define MSC_CLOCK_SOURCE X1000_CLK_MPLL
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{
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.msc_nr = 0,
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.msc_type = MSC_TYPE_SD,
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.bus_width = 4,
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.label = "microSD",
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.cd_gpio = GPIO_MSC0_CD,
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.cd_active_level = 0,
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},
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/* NOTE: SDIO wifi card is on msc1 */
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#elif defined(EROS_QN)
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#define MSC_CLOCK_SOURCE X1000_CLK_SCLK_A
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{
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.msc_nr = 0,
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.msc_type = MSC_TYPE_SD,
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.bus_width = 4,
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.label = "microSD",
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.cd_gpio = GPIO_MSC0_CD,
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.cd_active_level = 0,
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},
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#else
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# error "Please add X1000 MSC config"
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#endif
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{.msc_nr = -1},
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};
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static const msc_config* msc_lookup_config(int msc)
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{
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for(int i = 0; i < MSC_COUNT; ++i)
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if(msc_configs[i].msc_nr == msc)
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return &msc_configs[i];
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return NULL;
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}
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static msc_drv msc_drivers[MSC_COUNT];
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static void msc0_cd_interrupt(void);
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static void msc1_cd_interrupt(void);
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/* ---------------------------------------------------------------------------
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* Initialization
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*/
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static void msc_gate_clock(int msc, bool gate)
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{
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int bit;
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if(msc == 0)
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bit = BM_CPM_CLKGR_MSC0;
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else
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bit = BM_CPM_CLKGR_MSC1;
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if(gate)
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REG_CPM_CLKGR |= bit;
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else
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REG_CPM_CLKGR &= ~bit;
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}
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static void msc_init_one(msc_drv* d, int msc)
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{
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/* Lookup config */
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d->drive_nr = -1;
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d->config = msc_lookup_config(msc);
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if(!d->config) {
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d->msc_nr = -1;
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return;
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}
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/* Initialize driver state */
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d->msc_nr = msc;
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d->driver_flags = 0;
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d->clk_status = 0;
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d->cmdat_def = jz_orf(MSC_CMDAT, RTRG_V(GE32), TTRG_V(LE32));
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d->req = NULL;
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d->iflag_done = 0;
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d->card_present = 1;
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d->card_present_last = 1;
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d->req_running = 0;
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mutex_init(&d->lock);
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semaphore_init(&d->cmd_done, 1, 0);
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/* Ensure correct clock source */
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jz_writef(CPM_MSC0CDR, CE(1), CLKDIV(0),
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CLKSRC(MSC_CLOCK_SOURCE == X1000_CLK_MPLL ? 1 : 0));
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while(jz_readf(CPM_MSC0CDR, BUSY));
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jz_writef(CPM_MSC0CDR, CE(0));
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/* Initialize the hardware */
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msc_gate_clock(msc, false);
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msc_full_reset(d);
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system_enable_irq(msc == 0 ? IRQ_MSC0 : IRQ_MSC1);
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/* Setup the card detect IRQ */
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if(d->config->cd_gpio != GPIO_NONE) {
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if(gpio_get_level(d->config->cd_gpio) != d->config->cd_active_level) {
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d->card_present = 0;
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d->card_present_last = 0;
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}
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system_set_irq_handler(GPIO_TO_IRQ(d->config->cd_gpio),
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msc == 0 ? msc0_cd_interrupt : msc1_cd_interrupt);
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gpio_set_function(d->config->cd_gpio, GPIOF_IRQ_EDGE(1));
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gpio_flip_edge_irq(d->config->cd_gpio);
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gpio_enable_irq(d->config->cd_gpio);
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}
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}
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void msc_init(void)
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{
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/* Only do this once -- each storage subsystem calls us in its init */
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static bool done = false;
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if(done)
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return;
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done = true;
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/* Set up each MSC driver according to msc_configs */
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for(int i = 0; i < MSC_COUNT; ++i)
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msc_init_one(&msc_drivers[i], i);
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}
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msc_drv* msc_get(int type, int index)
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{
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for(int i = 0, m = 0; i < MSC_COUNT; ++i) {
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if(msc_drivers[i].config == NULL)
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continue;
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if(type == MSC_TYPE_ANY || msc_drivers[i].config->msc_type == type)
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if(index == m++)
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return &msc_drivers[i];
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}
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return NULL;
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}
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msc_drv* msc_get_by_drive(int drive_nr)
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{
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for(int i = 0; i < MSC_COUNT; ++i)
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if(msc_drivers[i].drive_nr == drive_nr)
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return &msc_drivers[i];
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return NULL;
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}
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void msc_lock(msc_drv* d)
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{
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mutex_lock(&d->lock);
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}
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void msc_unlock(msc_drv* d)
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{
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mutex_unlock(&d->lock);
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}
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void msc_full_reset(msc_drv* d)
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{
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msc_lock(d);
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msc_set_clock_mode(d, MSC_CLK_AUTOMATIC);
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msc_set_speed(d, MSC_SPEED_INIT);
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msc_set_width(d, 1);
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msc_ctl_reset(d);
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d->driver_flags = 0;
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memset(&d->cardinfo, 0, sizeof(tCardInfo));
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msc_unlock(d);
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}
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bool msc_card_detect(msc_drv* d)
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{
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if(d->config->cd_gpio == GPIO_NONE)
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return true;
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return gpio_get_level(d->config->cd_gpio) == d->config->cd_active_level;
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}
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void msc_led_trigger(void)
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{
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bool state = false;
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for(int i = 0; i < MSC_COUNT; ++i)
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if(msc_drivers[i].req_running)
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state = true;
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led(state);
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}
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/* ---------------------------------------------------------------------------
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* Controller API
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*/
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void msc_ctl_reset(msc_drv* d)
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{
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/* Ingenic code suggests a reset changes clkrt */
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int clkrt = REG_MSC_CLKRT(d->msc_nr);
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/* Send reset -- bit is NOT self clearing */
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jz_overwritef(MSC_CTRL(d->msc_nr), RESET(1));
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udelay(100);
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jz_writef(MSC_CTRL(d->msc_nr), RESET(0));
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/* Verify reset in the status register */
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long deadline = current_tick + HZ;
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while(jz_readf(MSC_STAT(d->msc_nr), IS_RESETTING) &&
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current_tick < deadline) {
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sleep(1);
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}
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/* Ensure the clock state is as expected */
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if(d->clk_status & MSC_CLKST_AUTO)
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jz_writef(MSC_LPM(d->msc_nr), ENABLE(1));
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else if(d->clk_status & MSC_CLKST_ENABLE)
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jz_overwritef(MSC_CTRL(d->msc_nr), CLOCK_V(START));
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else
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jz_overwritef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP));
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/* Clear and mask interrupts */
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REG_MSC_IMASK(d->msc_nr) = 0xffffffff;
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REG_MSC_IFLAG(d->msc_nr) = 0xffffffff;
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/* Restore clkrt */
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REG_MSC_CLKRT(d->msc_nr) = clkrt;
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}
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void msc_set_clock_mode(msc_drv* d, int mode)
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{
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int cur_mode = (d->clk_status & MSC_CLKST_AUTO) ? MSC_CLK_AUTOMATIC
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: MSC_CLK_MANUAL;
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if(mode == cur_mode)
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return;
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d->clk_status &= ~MSC_CLKST_ENABLE;
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if(mode == MSC_CLK_AUTOMATIC) {
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d->clk_status |= MSC_CLKST_AUTO;
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP));
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jz_writef(MSC_LPM(d->msc_nr), ENABLE(1));
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} else {
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d->clk_status &= ~MSC_CLKST_AUTO;
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jz_writef(MSC_LPM(d->msc_nr), ENABLE(0));
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP));
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}
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}
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void msc_enable_clock(msc_drv* d, bool enable)
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{
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if(d->clk_status & MSC_CLKST_AUTO)
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return;
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bool is_enabled = (d->clk_status & MSC_CLKST_ENABLE);
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if(enable == is_enabled)
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return;
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if(enable) {
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(START));
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d->clk_status |= MSC_CLKST_ENABLE;
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} else {
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP));
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d->clk_status &= ~MSC_CLKST_ENABLE;
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}
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}
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void msc_set_speed(msc_drv* d, int rate)
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{
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/* Shut down clock while we change frequencies */
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if(d->clk_status & MSC_CLKST_ENABLE)
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(STOP));
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/* Wait for clock to go idle */
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while(jz_readf(MSC_STAT(d->msc_nr), CLOCK_EN))
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sleep(1);
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/* freq1 is output by MSCxDIV; freq2 is output by MSC_CLKRT */
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uint32_t freq1 = rate;
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uint32_t freq2 = rate;
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if(freq1 < MSC_SPEED_FAST)
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freq1 = MSC_SPEED_FAST;
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/* Handle MSCxDIV */
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uint32_t src_freq = clk_get(MSC_CLOCK_SOURCE) / 2;
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uint32_t div = clk_calc_div(src_freq, freq1);
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if(d->msc_nr == 0) {
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jz_writef(CPM_MSC0CDR, CE(1), CLKDIV(div - 1));
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while(jz_readf(CPM_MSC0CDR, BUSY));
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jz_writef(CPM_MSC0CDR, CE(0));
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} else {
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jz_writef(CPM_MSC1CDR, CE(1), CLKDIV(div - 1));
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while(jz_readf(CPM_MSC1CDR, BUSY));
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jz_writef(CPM_MSC1CDR, CE(0));
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}
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/* Handle MSC_CLKRT */
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uint32_t clkrt = clk_calc_shift(src_freq/div, freq2);
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REG_MSC_CLKRT(d->msc_nr) = clkrt;
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/* Handle frequency dependent timing settings
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* TODO - these settings might be SD specific...
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*/
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uint32_t out_freq = (src_freq/div) >> clkrt;
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if(out_freq > MSC_SPEED_FAST) {
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jz_writef(MSC_LPM(d->msc_nr),
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DRV_SEL_V(RISE_EDGE_DELAY_QTR_PHASE),
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SMP_SEL_V(RISE_EDGE_DELAYED));
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jz_writef(MSC_CTRL2(d->msc_nr), SPEED_V(HIGHSPEED));
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} else {
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jz_writef(MSC_LPM(d->msc_nr),
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DRV_SEL_V(FALL_EDGE),
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SMP_SEL_V(RISE_EDGE));
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jz_writef(MSC_CTRL2(d->msc_nr), SPEED_V(DEFAULT));
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}
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/* Restart clock if it was running before */
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if(d->clk_status & MSC_CLKST_ENABLE)
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jz_writef(MSC_CTRL(d->msc_nr), CLOCK_V(START));
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}
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void msc_set_width(msc_drv* d, int width)
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{
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/* Bus width is controlled per command with MSC_CMDAT. */
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if(width == 8)
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jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(8BIT));
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else if(width == 4)
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jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(4BIT));
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else
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jz_vwritef(d->cmdat_def, MSC_CMDAT, BUS_WIDTH_V(1BIT));
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}
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/* ---------------------------------------------------------------------------
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* Request API
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*/
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/* Note -- this must only be called with IRQs disabled */
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static void msc_finish_request(msc_drv* d, int status)
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{
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REG_MSC_IMASK(d->msc_nr) = 0xffffffff;
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REG_MSC_IFLAG(d->msc_nr) = 0xffffffff;
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if(d->req->flags & MSC_RF_DATA)
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jz_writef(MSC_DMAC(d->msc_nr), ENABLE(0));
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d->req->status = status;
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d->req_running = 0;
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d->iflag_done = 0;
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msc_led_trigger();
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timeout_cancel(&d->cmd_tmo);
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semaphore_release(&d->cmd_done);
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}
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static int msc_req_timeout(struct timeout* tmo)
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{
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msc_drv* d = (msc_drv*)tmo->data;
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msc_async_abort(d, MSC_REQ_LOCKUP);
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return 0;
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}
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void msc_async_start(msc_drv* d, msc_req* r)
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{
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/* Determined needed cmdat and interrupts */
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unsigned cmdat = d->cmdat_def;
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d->iflag_done = jz_orm(MSC_IFLAG, END_CMD_RES);
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cmdat |= jz_orf(MSC_CMDAT, RESP_FMT(r->resptype & ~MSC_RESP_BUSY));
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if(r->resptype & MSC_RESP_BUSY)
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cmdat |= jz_orm(MSC_CMDAT, BUSY);
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if(r->flags & MSC_RF_INIT)
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cmdat |= jz_orm(MSC_CMDAT, INIT);
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if(r->flags & MSC_RF_DATA) {
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cmdat |= jz_orm(MSC_CMDAT, DATA_EN);
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if(r->flags & MSC_RF_PROG)
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d->iflag_done = jz_orm(MSC_IFLAG, WR_ALL_DONE);
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else
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d->iflag_done = jz_orm(MSC_IFLAG, DMA_DATA_DONE);
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}
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if(r->flags & MSC_RF_WRITE)
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cmdat |= jz_orm(MSC_CMDAT, WRITE_READ);
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if(r->flags & MSC_RF_AUTO_CMD12)
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cmdat |= jz_orm(MSC_CMDAT, AUTO_CMD12);
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if(r->flags & MSC_RF_ABORT)
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cmdat |= jz_orm(MSC_CMDAT, IO_ABORT);
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unsigned imask = jz_orm(MSC_IMASK,
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CRC_RES_ERROR, CRC_READ_ERROR, CRC_WRITE_ERROR,
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TIME_OUT_RES, TIME_OUT_READ, END_CMD_RES);
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imask |= d->iflag_done;
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/* Program the controller */
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if(r->flags & MSC_RF_DATA) {
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REG_MSC_NOB(d->msc_nr) = r->nr_blocks;
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REG_MSC_BLKLEN(d->msc_nr) = r->block_len;
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}
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REG_MSC_CMD(d->msc_nr) = r->command;
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REG_MSC_ARG(d->msc_nr) = r->argument;
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REG_MSC_CMDAT(d->msc_nr) = cmdat;
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REG_MSC_IFLAG(d->msc_nr) = imask;
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REG_MSC_IMASK(d->msc_nr) &= ~imask;
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if(r->flags & MSC_RF_DATA) {
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d->dma_desc.nda = 0;
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d->dma_desc.mem = PHYSADDR(r->data);
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d->dma_desc.len = r->nr_blocks * r->block_len;
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d->dma_desc.cmd = 2; /* ID=0, ENDI=1, LINK=0 */
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commit_dcache_range(&d->dma_desc, sizeof(d->dma_desc));
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if(r->flags & MSC_RF_WRITE)
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commit_dcache_range(r->data, d->dma_desc.len);
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else
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discard_dcache_range(r->data, d->dma_desc.len);
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/* Unaligned address for DMA doesn't seem to work correctly.
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* FAT FS driver should ensure proper alignment of all buffers,
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* so in practice this panic should not occur, but if it does
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* I want to hear about it. */
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if(UNLIKELY(d->dma_desc.mem & 3)) {
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panicf("msc%d bad align: %08x", d->msc_nr,
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(unsigned)d->dma_desc.mem);
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}
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|
|
jz_writef(MSC_DMAC(d->msc_nr), MODE_SEL(0), INCR(0), DMASEL(0));
|
|
REG_MSC_DMANDA(d->msc_nr) = PHYSADDR(&d->dma_desc);
|
|
}
|
|
|
|
/* Begin processing */
|
|
d->req = r;
|
|
d->req_running = 1;
|
|
msc_led_trigger();
|
|
jz_writef(MSC_CTRL(d->msc_nr), START_OP(1));
|
|
if(r->flags & MSC_RF_DATA)
|
|
jz_writef(MSC_DMAC(d->msc_nr), ENABLE(1));
|
|
|
|
/* TODO: calculate a suitable lower value for the lockup timeout.
|
|
*
|
|
* The SD spec defines timings based on the number of blocks transferred,
|
|
* see sec. 4.6.2 "Read, write, and erase timeout conditions". This should
|
|
* reduce the long delays which happen if errors occur.
|
|
*
|
|
* Also need to check if registers MSC_RDTO / MSC_RESTO are correctly set.
|
|
*/
|
|
timeout_register(&d->cmd_tmo, msc_req_timeout, 10*HZ, (intptr_t)d);
|
|
}
|
|
|
|
void msc_async_abort(msc_drv* d, int status)
|
|
{
|
|
int irq = disable_irq_save();
|
|
if(d->req_running) {
|
|
logf("msc%d: async abort status:%d", d->msc_nr, status);
|
|
msc_finish_request(d, status);
|
|
}
|
|
|
|
restore_irq(irq);
|
|
}
|
|
|
|
int msc_async_wait(msc_drv* d, int timeout)
|
|
{
|
|
if(semaphore_wait(&d->cmd_done, timeout) == OBJ_WAIT_TIMEDOUT)
|
|
return MSC_REQ_INCOMPLETE;
|
|
|
|
return d->req->status;
|
|
}
|
|
|
|
int msc_request(msc_drv* d, msc_req* r)
|
|
{
|
|
msc_async_start(d, r);
|
|
return msc_async_wait(d, TIMEOUT_BLOCK);
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------------
|
|
* Command response handling
|
|
*/
|
|
|
|
static void msc_read_response(msc_drv* d)
|
|
{
|
|
unsigned res = REG_MSC_RES(d->msc_nr);
|
|
unsigned dat;
|
|
switch(d->req->resptype) {
|
|
case MSC_RESP_R1:
|
|
case MSC_RESP_R1B:
|
|
case MSC_RESP_R3:
|
|
case MSC_RESP_R6:
|
|
case MSC_RESP_R7:
|
|
dat = res << 24;
|
|
res = REG_MSC_RES(d->msc_nr);
|
|
dat |= res << 8;
|
|
res = REG_MSC_RES(d->msc_nr);
|
|
dat |= res & 0xff;
|
|
d->req->response[0] = dat;
|
|
break;
|
|
|
|
case MSC_RESP_R2:
|
|
for(int i = 0; i < 4; ++i) {
|
|
dat = res << 24;
|
|
res = REG_MSC_RES(d->msc_nr);
|
|
dat |= res << 8;
|
|
res = REG_MSC_RES(d->msc_nr);
|
|
dat |= res >> 8;
|
|
d->req->response[i] = dat;
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int msc_check_sd_response(msc_drv* d)
|
|
{
|
|
if(d->req->resptype == MSC_RESP_R1 ||
|
|
d->req->resptype == MSC_RESP_R1B) {
|
|
if(d->req->response[0] & SD_R1_CARD_ERROR) {
|
|
logf("msc%d: R1 card error: %08x", d->msc_nr, d->req->response[0]);
|
|
return MSC_REQ_CARD_ERR;
|
|
}
|
|
}
|
|
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
static int msc_check_response(msc_drv* d)
|
|
{
|
|
switch(d->config->msc_type) {
|
|
case MSC_TYPE_SD:
|
|
return msc_check_sd_response(d);
|
|
default:
|
|
/* TODO - implement msc_check_response for MMC and CE-ATA */
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------------
|
|
* Interrupt handlers
|
|
*/
|
|
|
|
static void msc_interrupt(msc_drv* d)
|
|
{
|
|
const unsigned tmo_bits = jz_orm(MSC_IFLAG, TIME_OUT_READ, TIME_OUT_RES);
|
|
const unsigned crc_bits = jz_orm(MSC_IFLAG, CRC_RES_ERROR,
|
|
CRC_READ_ERROR, CRC_WRITE_ERROR);
|
|
const unsigned err_bits = tmo_bits | crc_bits;
|
|
|
|
unsigned iflag = REG_MSC_IFLAG(d->msc_nr) & ~REG_MSC_IMASK(d->msc_nr);
|
|
bool handled = false;
|
|
|
|
/* In case card was removed */
|
|
if(!msc_card_detect(d)) {
|
|
msc_finish_request(d, MSC_REQ_EXTRACTED);
|
|
return;
|
|
}
|
|
|
|
/* Check for errors */
|
|
if(iflag & err_bits) {
|
|
int st;
|
|
if(iflag & crc_bits)
|
|
st = MSC_REQ_CRC_ERR;
|
|
else if(iflag & tmo_bits)
|
|
st = MSC_REQ_TIMEOUT;
|
|
else
|
|
st = MSC_REQ_ERROR;
|
|
|
|
msc_finish_request(d, st);
|
|
return;
|
|
}
|
|
|
|
/* Read and check the command response */
|
|
if(iflag & BM_MSC_IFLAG_END_CMD_RES) {
|
|
msc_read_response(d);
|
|
int st = msc_check_response(d);
|
|
if(st == MSC_REQ_SUCCESS) {
|
|
jz_writef(MSC_IMASK(d->msc_nr), END_CMD_RES(1));
|
|
jz_overwritef(MSC_IFLAG(d->msc_nr), END_CMD_RES(1));
|
|
handled = true;
|
|
} else {
|
|
msc_finish_request(d, st);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Check if the "done" interrupt is signaled */
|
|
if(iflag & d->iflag_done) {
|
|
/* Discard after DMA in case of hardware cache prefetching.
|
|
* Only needed for read operations.
|
|
*/
|
|
if((d->req->flags & MSC_RF_DATA) != 0 &&
|
|
(d->req->flags & MSC_RF_WRITE) == 0) {
|
|
discard_dcache_range(d->req->data,
|
|
d->req->block_len * d->req->nr_blocks);
|
|
}
|
|
|
|
msc_finish_request(d, MSC_REQ_SUCCESS);
|
|
return;
|
|
}
|
|
|
|
if(!handled) {
|
|
panicf("msc%d: irq bug! iflag:%08x raw_iflag:%08lx imask:%08lx",
|
|
d->msc_nr, iflag, REG_MSC_IFLAG(d->msc_nr), REG_MSC_IMASK(d->msc_nr));
|
|
}
|
|
}
|
|
|
|
static int msc_cd_callback(struct timeout* tmo)
|
|
{
|
|
msc_drv* d = (msc_drv*)tmo->data;
|
|
int now_present = msc_card_detect(d) ? 1 : 0;
|
|
|
|
/* If the CD pin level changed during the timeout interval, then the
|
|
* signal is not yet stable and we need to wait longer. */
|
|
if(now_present != d->card_present_last) {
|
|
d->card_present_last = now_present;
|
|
return DEBOUNCE_TIME;
|
|
}
|
|
|
|
/* If there is a change, then broadcast the hotswap event */
|
|
if(now_present != d->card_present) {
|
|
if(now_present) {
|
|
d->card_present = 1;
|
|
queue_broadcast(SYS_HOTSWAP_INSERTED, d->drive_nr);
|
|
} else {
|
|
msc_async_abort(d, MSC_REQ_EXTRACTED);
|
|
d->card_present = 0;
|
|
queue_broadcast(SYS_HOTSWAP_EXTRACTED, d->drive_nr);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void msc_cd_interrupt(msc_drv* d)
|
|
{
|
|
/* Timer to debounce input */
|
|
d->card_present_last = msc_card_detect(d) ? 1 : 0;
|
|
timeout_register(&d->cd_tmo, msc_cd_callback, DEBOUNCE_TIME, (intptr_t)d);
|
|
|
|
/* Invert the IRQ */
|
|
gpio_flip_edge_irq(d->config->cd_gpio);
|
|
}
|
|
|
|
void MSC0(void)
|
|
{
|
|
msc_interrupt(&msc_drivers[0]);
|
|
}
|
|
|
|
void MSC1(void)
|
|
{
|
|
msc_interrupt(&msc_drivers[1]);
|
|
}
|
|
|
|
static void msc0_cd_interrupt(void)
|
|
{
|
|
msc_cd_interrupt(&msc_drivers[0]);
|
|
}
|
|
|
|
static void msc1_cd_interrupt(void)
|
|
{
|
|
msc_cd_interrupt(&msc_drivers[1]);
|
|
}
|
|
|
|
/* ---------------------------------------------------------------------------
|
|
* SD command helpers
|
|
*/
|
|
|
|
int msc_cmd_exec(msc_drv* d, msc_req* r)
|
|
{
|
|
int status = msc_request(d, r);
|
|
if(status == MSC_REQ_SUCCESS)
|
|
return status;
|
|
else if(status == MSC_REQ_LOCKUP || status == MSC_REQ_EXTRACTED)
|
|
d->driver_flags |= MSC_DF_ERRSTATE;
|
|
else if(r->flags & (MSC_RF_ERR_CMD12|MSC_RF_AUTO_CMD12)) {
|
|
/* After an error, the controller does not automatically issue CMD12,
|
|
* so we need to send it if it's needed, as required by the SD spec.
|
|
*/
|
|
msc_req nreq = {0};
|
|
nreq.command = SD_STOP_TRANSMISSION;
|
|
nreq.resptype = MSC_RESP_R1B;
|
|
nreq.flags = MSC_RF_ABORT;
|
|
logf("msc%d: cmd%d error, sending cmd12", d->msc_nr, r->command);
|
|
if(msc_cmd_exec(d, &nreq))
|
|
d->driver_flags |= MSC_DF_ERRSTATE;
|
|
}
|
|
|
|
logf("msc%d: err:%d, cmd%d, arg:%x", d->msc_nr, status,
|
|
r->command, r->argument);
|
|
return status;
|
|
}
|
|
|
|
int msc_app_cmd_exec(msc_drv* d, msc_req* r)
|
|
{
|
|
msc_req areq = {0};
|
|
areq.command = SD_APP_CMD;
|
|
areq.argument = d->cardinfo.rca;
|
|
areq.resptype = MSC_RESP_R1;
|
|
if(msc_cmd_exec(d, &areq))
|
|
return areq.status;
|
|
|
|
/* Verify that CMD55 was accepted */
|
|
if((areq.response[0] & (1 << 5)) == 0)
|
|
return MSC_REQ_ERROR;
|
|
|
|
return msc_cmd_exec(d, r);
|
|
}
|
|
|
|
int msc_cmd_go_idle_state(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_GO_IDLE_STATE;
|
|
req.resptype = MSC_RESP_NONE;
|
|
req.flags = MSC_RF_INIT;
|
|
return msc_cmd_exec(d, &req);
|
|
}
|
|
|
|
int msc_cmd_send_if_cond(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SEND_IF_COND;
|
|
req.argument = 0x1aa;
|
|
req.resptype = MSC_RESP_R7;
|
|
|
|
/* TODO - Check if SEND_IF_COND timeout is really an error
|
|
* IIRC, this can occur if the card isn't HCS (old cards < 2 GiB).
|
|
*/
|
|
if(msc_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
/* Set HCS bit if the card responds correctly */
|
|
if((req.response[0] & 0xff) == 0xaa)
|
|
d->driver_flags |= MSC_DF_HCS_CARD;
|
|
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_app_op_cond(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_APP_OP_COND;
|
|
req.argument = 0x00300000; /* 3.4 - 3.6 V */
|
|
req.resptype = MSC_RESP_R3;
|
|
if(d->driver_flags & MSC_DF_HCS_CARD)
|
|
req.argument |= (1 << 30);
|
|
|
|
int timeout = 2 * HZ;
|
|
do {
|
|
if(msc_app_cmd_exec(d, &req))
|
|
return req.status;
|
|
if(req.response[0] & (1 << 31))
|
|
break;
|
|
sleep(1);
|
|
} while(--timeout > 0);
|
|
|
|
if(timeout == 0)
|
|
return MSC_REQ_TIMEOUT;
|
|
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_all_send_cid(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_ALL_SEND_CID;
|
|
req.resptype = MSC_RESP_R2;
|
|
if(msc_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
for(int i = 0; i < 4; ++i)
|
|
d->cardinfo.cid[i] = req.response[i];
|
|
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_send_rca(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SEND_RELATIVE_ADDR;
|
|
req.resptype = MSC_RESP_R6;
|
|
if(msc_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
d->cardinfo.rca = req.response[0] & 0xffff0000;
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_send_csd(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SEND_CSD;
|
|
req.argument = d->cardinfo.rca;
|
|
req.resptype = MSC_RESP_R2;
|
|
if(msc_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
for(int i = 0; i < 4; ++i)
|
|
d->cardinfo.csd[i] = req.response[i];
|
|
sd_parse_csd(&d->cardinfo);
|
|
|
|
if((req.response[0] >> 30) == 1)
|
|
d->driver_flags |= MSC_DF_V2_CARD;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int msc_cmd_select_card(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SELECT_CARD;
|
|
req.argument = d->cardinfo.rca;
|
|
req.resptype = MSC_RESP_R1B;
|
|
return msc_cmd_exec(d, &req);
|
|
}
|
|
|
|
int msc_cmd_set_bus_width(msc_drv* d, int width)
|
|
{
|
|
/* TODO - must we check bus width is supported in the cardinfo? */
|
|
msc_req req = {0};
|
|
req.command = SD_SET_BUS_WIDTH;
|
|
req.resptype = MSC_RESP_R1;
|
|
switch(width) {
|
|
case 1: req.argument = 0; break;
|
|
case 4: req.argument = 2; break;
|
|
default: return MSC_REQ_ERROR;
|
|
}
|
|
|
|
if(msc_app_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
msc_set_width(d, width);
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_set_clr_card_detect(msc_drv* d, int arg)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SET_CLR_CARD_DETECT;
|
|
req.argument = arg;
|
|
req.resptype = MSC_RESP_R1;
|
|
return msc_app_cmd_exec(d, &req);
|
|
}
|
|
|
|
int msc_cmd_switch_freq(msc_drv* d)
|
|
{
|
|
/* If card doesn't support High Speed, we don't need to send a command */
|
|
if((d->driver_flags & MSC_DF_V2_CARD) == 0) {
|
|
msc_set_speed(d, MSC_SPEED_FAST);
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
/* Try switching to High Speed (50 MHz) */
|
|
char buffer[64] CACHEALIGN_ATTR;
|
|
msc_req req = {0};
|
|
req.command = SD_SWITCH_FUNC;
|
|
req.argument = 0x80fffff1;
|
|
req.resptype = MSC_RESP_R1;
|
|
req.flags = MSC_RF_DATA;
|
|
req.data = &buffer[0];
|
|
req.block_len = 64;
|
|
req.nr_blocks = 1;
|
|
if(msc_cmd_exec(d, &req))
|
|
return req.status;
|
|
|
|
msc_set_speed(d, MSC_SPEED_HIGH);
|
|
return MSC_REQ_SUCCESS;
|
|
}
|
|
|
|
int msc_cmd_send_status(msc_drv* d)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SEND_STATUS;
|
|
req.argument = d->cardinfo.rca;
|
|
req.resptype = MSC_RESP_R1;
|
|
return msc_cmd_exec(d, &req);
|
|
}
|
|
|
|
int msc_cmd_set_block_len(msc_drv* d, unsigned len)
|
|
{
|
|
msc_req req = {0};
|
|
req.command = SD_SET_BLOCKLEN;
|
|
req.argument = len;
|
|
req.resptype = MSC_RESP_R1;
|
|
return msc_cmd_exec(d, &req);
|
|
}
|