175 lines
4.9 KiB
C
175 lines
4.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "aic-x1000.h"
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#include "gpio-x1000.h"
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#include "x1000/aic.h"
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#include "x1000/cpm.h"
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/* Given a rational number m/n < 1, find its representation as a continued
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* fraction [0; a1, a2, a3, ..., a_k]. At most "cnt" terms are calculated
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* and written out to "buf". Returns the number of terms written; the result
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* is complete if this value is less than "cnt", and may be incomplete if it
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* is equal to "cnt". (Note the leading zero term is not written to "buf".)
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*/
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static uint32_t cf_derive(uint32_t m, uint32_t n, uint32_t* buf, uint32_t cnt)
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{
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uint32_t wrote = 0;
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uint32_t a = m / n;
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while(cnt--) {
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uint32_t tmp = n;
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n = m - n * a;
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if(n == 0)
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break;
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m = tmp;
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a = m / n;
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*buf++ = a;
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wrote++;
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}
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return wrote;
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}
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/* Given a finite continued fraction [0; buf[0], buf[1], ..., buf[count-1]],
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* calculate the rational number m/n which it represents. Returns m and n.
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* If count is zero, then m and n are undefined.
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*/
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static void cf_expand(const uint32_t* buf, uint32_t count,
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uint32_t* m, uint32_t* n)
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{
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if(count == 0)
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return;
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uint32_t i = count - 1;
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uint32_t mx = 1, nx = buf[i];
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while(i--) {
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uint32_t tmp = nx;
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nx = mx + buf[i] * nx;
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mx = tmp;
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}
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*m = mx;
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*n = nx;
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}
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static int calc_i2s_clock_params(x1000_clk_t clksrc,
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uint32_t fs, uint32_t mult,
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uint32_t* div_m, uint32_t* div_n,
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uint32_t* i2sdiv)
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{
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if(clksrc == X1000_CLK_EXCLK) {
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/* EXCLK mode bypasses the CPM clock so it's more limited */
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*div_m = 0;
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*div_n = 0;
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*i2sdiv = X1000_EXCLK_FREQ / 64 / fs;
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/* clamp to maximum value */
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if(*i2sdiv > 512)
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*i2sdiv = 512;
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if(*i2sdiv == 0)
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*i2sdiv = 1;
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return 0;
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}
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/* ensure a valid clock was selected */
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if(clksrc != X1000_CLK_SCLK_A &&
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clksrc != X1000_CLK_MPLL)
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return -1;
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/* ensure bit clock constraint is respected */
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if(mult % 64 != 0)
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return -1;
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/* ensure master clock frequency is not too high */
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if(fs > UINT32_MAX/mult)
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return -1;
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/* get frequencies */
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uint32_t tgt_freq = fs * mult;
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uint32_t src_freq = clk_get(clksrc);
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/* calculate best rational approximation fitting hardware constraints */
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uint32_t m = 0, n = 0;
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uint32_t buf[16];
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uint32_t cnt = cf_derive(tgt_freq, src_freq, &buf[0], 16);
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do {
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cf_expand(&buf[0], cnt, &m, &n);
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cnt -= 1;
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} while(cnt > 0 && (m > 512 || n > 8192) && (n >= 2*m));
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/* unrepresentable */
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if(cnt == 0 || n == 0 || m == 0)
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return -1;
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*div_m = m;
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*div_n = n;
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*i2sdiv = mult / 64;
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return 0;
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}
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uint32_t aic_calc_i2s_clock(x1000_clk_t clksrc, uint32_t fs, uint32_t mult)
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{
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uint32_t m, n, i2sdiv;
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if(calc_i2s_clock_params(clksrc, fs, mult, &m, &n, &i2sdiv))
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return 0;
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unsigned long long rate = clk_get(clksrc);
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rate *= m;
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rate /= n * i2sdiv; /* this multiply can't overflow. */
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/* clamp */
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if(rate > 0xffffffffull)
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rate = 0xffffffff;
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return rate;
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}
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int aic_set_i2s_clock(x1000_clk_t clksrc, uint32_t fs, uint32_t mult)
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{
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uint32_t m, n, i2sdiv;
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if(calc_i2s_clock_params(clksrc, fs, mult, &m, &n, &i2sdiv))
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return -1;
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/* turn off bit clock */
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bool bitclock_en = !jz_readf(AIC_I2SCR, STPBK);
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jz_writef(AIC_I2SCR, STPBK(1));
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/* handle master clock */
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if(clksrc == X1000_CLK_EXCLK) {
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jz_writef(CPM_I2SCDR, CS(0), CE(0));
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} else {
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jz_writef(CPM_I2SCDR, PCS(clksrc == X1000_CLK_MPLL ? 1 : 0),
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CS(1), CE(1), DIV_M(m), DIV_N(n));
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jz_write(CPM_I2SCDR1, REG_CPM_I2SCDR1);
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}
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/* set bit clock divider */
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REG_AIC_I2SDIV = i2sdiv - 1;
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/* re-enable the bit clock */
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if(bitclock_en)
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jz_writef(AIC_I2SCR, STPBK(0));
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return 0;
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}
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