440 lines
13 KiB
C
440 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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* Copyright (C) 2005 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdlib.h>
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#include "system.h"
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#include "kernel.h"
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#include "logf.h"
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#include "audio.h"
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#include "sound.h"
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#if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
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#include "spdif.h"
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#endif
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#include "pcm-internal.h"
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#define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
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(IIS_PLAY & (7 << 8)) | \
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(4 << 2) ) /* 64 bit clocks / word clock */
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#define IIS_FIFO_RESET (1 << 11)
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#define PDIR2_FIFO_RESET (1 << 9)
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#if defined(IAUDIO_X5) || defined(IAUDIO_M5) || defined(IAUDIO_M3)
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#define IIS_PLAY IIS1CONFIG
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#else
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#define IIS_PLAY IIS2CONFIG
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#endif
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#ifdef HAVE_SPDIF_OUT
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/* EBU TX auto sync, PDIR2 fifo auto sync, IIS1 fifo auto sync */
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#define AUDIOGLOB_DEFPARM ((1 << 10) | (1 << 8) | (1 << 7))
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#else
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/* PDIR2 fifo auto sync, IIS1 fifo auto sync */
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#define AUDIOGLOB_DEFPARM ((1 << 8) | (1 << 7))
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#endif
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/** Sample rates **/
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#define PLLCR_SET_AUDIO_BITS_DEFPARM \
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((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
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#define FPARM_CLOCKSEL 0
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#define FPARM_CLSEL 1
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/* SCLK = Fs * bit clocks per word
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* so SCLK should be Fs * 64
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*
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* CLOCKSEL sets SCLK freq based on Audio CLK
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* 0x0c SCLK = Audio CLK/2 88200 * 64 = 5644800 Hz
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* 0x06 SCLK = Audio CLK/4 44100 * 64 = 2822400 Hz
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* 0x04 SCLK = Audio CLK/8 22050 * 64 = 1411200 Hz
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* 0x02 SCLK = Audio CLK/16 11025 * 64 = 705600 Hz
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*
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* CLSEL sets MCLK1/2 DAC freq based on XTAL freq
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* 0x01 MCLK1/2 = XTAL freq
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* 0x02 MCLK1/2 = XTAL/2 freq
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*
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* Audio CLK can be XTAL freq or XTAL/2 freq (bit22 in PLLCR)
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* we always set bit22 so Audio CLK is always XTAL freq
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*/
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#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
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{
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HW_HAVE_88_([HW_FREQ_88] = { 0x0c, 0x01 },)
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[HW_FREQ_44] = { 0x06, 0x01 },
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[HW_FREQ_22] = { 0x04, 0x02 },
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[HW_FREQ_11] = { 0x02, 0x02 },
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};
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#endif
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#if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750)
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/* We run codec in master mode.
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* Codec can reconstruct all frequencies
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* from single 11.2896 MHz master clock
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*/
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
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{
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HW_HAVE_88_([HW_FREQ_88] = { 0x00, 0x01 },)
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[HW_FREQ_44] = { 0x00, 0x01 },
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[HW_FREQ_22] = { 0x00, 0x01 },
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[HW_FREQ_11] = { 0x00, 0x01 },
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};
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#endif
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#if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320)
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static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
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{
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HW_HAVE_88_([HW_FREQ_88] = { 0x0c, 0x01 },)
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[HW_FREQ_44] = { 0x06, 0x01 },
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[HW_FREQ_22] = { 0x04, 0x01 },
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[HW_FREQ_11] = { 0x02, 0x02 },
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};
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#endif
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static const unsigned char *freq_ent;
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/* Lock status struct for playback and recording */
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struct dma_lock
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{
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int locked;
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unsigned long state;
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};
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static void iis_play_reset(void)
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{
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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and_l(~IIS_FIFO_RESET, &IIS_PLAY);
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PDOR3 = 0;
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}
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static bool is_playback_monitoring(void)
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{
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return (IIS_PLAY & (7 << 8)) == (3 << 8);
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}
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static void iis_play_reset_if_playback(bool if_playback)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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if (is_playback_monitoring() == if_playback)
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iis_play_reset();
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restore_irq(level);
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}
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/* apply audio settings */
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/* This clears the reset bit to enable monitoring immediately if monitoring
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recording sources or always if playback is in progress - we might be
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switching samplerates on the fly */
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void pcm_dma_apply_settings(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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/* remember table entry */
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freq_ent = pcm_freq_parms[pcm_fsel];
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/* Reprogramming bits 15-12 requires FIFO to be in a reset
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condition - Users Manual 17-8, Note 11 */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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/* Important for TLV320 - this must happen in the correct order
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or starting recording will sound absolutely awful once in
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awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
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*/
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IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
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restore_irq(level);
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audiohw_set_frequency(pcm_fsel);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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level = set_irq_level(DMA_IRQ_LEVEL);
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IIS_PLAY = IIS_PLAY_DEFPARM;
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if ((DCR0 & DMA_EEXT) != 0 && is_playback_monitoring())
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PDOR3 = 0; /* Kick FIFO out of reset by writing to it */
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restore_irq(level);
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} /* pcm_dma_apply_settings */
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void pcm_play_dma_init(void)
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{
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freq_ent = pcm_freq_parms[pcm_fsel];
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AUDIOGLOB = AUDIOGLOB_DEFPARM;
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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and_l(0xffffff00, &DMAROUTE);
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or_l(DMA0_REQ_AUDIO_1, &DMAROUTE);
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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BCR0 = 0; /* No bytes waiting */
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ICR6 = (6 << 2); /* Enable interrupt at level 6, priority 0 */
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/* Setup Coldfire I2S before initializing hardware or changing
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other settings. */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
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audio_set_output_source(AUDIO_SRC_PLAYBACK);
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/* Initialize default register values. */
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audiohw_init();
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audio_input_mux(AUDIO_SRC_PLAYBACK, SRCF_PLAYBACK);
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audiohw_set_frequency(pcm_fsel);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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#if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
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spdif_init();
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#endif
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} /* pcm_play_dma_init */
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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iis_play_reset();
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}
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/** DMA **/
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/****************************************************************************
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** Playback DMA transfer
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**/
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/* For the locks, DMA interrupt must be disabled when manipulating the lock
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if the handler ever calls these - right now things are arranged so it
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doesn't */
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static struct dma_lock dma_play_lock =
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{
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.locked = 0,
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.state = (1 << 14) /* bit 14 is DMA0 */
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};
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void pcm_play_lock(void)
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{
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if (++dma_play_lock.locked == 1)
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coldfire_imr_mod(1 << 14, 1 << 14);
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}
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void pcm_play_unlock(void)
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{
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if (--dma_play_lock.locked == 0)
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coldfire_imr_mod(dma_play_lock.state, 1 << 14);
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}
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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/* Stop any DMA in progress */
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pcm_play_dma_stop();
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/* Set up DMA transfer */
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SAR0 = (unsigned long)addr; /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = (unsigned long)size; /* Bytes to transfer */
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_SINC |
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DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
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dma_play_lock.state = (0 << 14);
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} /* pcm_play_dma_start */
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/* Stops the DMA transfer and interrupt */
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void pcm_play_dma_stop(void)
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{
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and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
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BCR0 = 0; /* No bytes remaining */
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DSR0 = 1; /* Clear interrupt, errors, stop transfer */
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iis_play_reset_if_playback(true);
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dma_play_lock.state = (1 << 14);
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} /* pcm_play_dma_stop */
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/* DMA0 Interrupt is called when the DMA has finished transfering a chunk
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from the caller's buffer */
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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unsigned long res = DSR0;
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and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
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DSR0 = 1; /* Clear interrupt and errors */
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if (res & 0x70)
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{
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logf("DMA0 err: %02x", res);
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#if 0
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logf(" SAR0: %08x", SAR0);
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logf(" DAR0: %08x", DAR0);
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logf(" BCR0: %08x", BCR0);
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logf(" DCR0: %08x", DCR0);
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#endif
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}
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const void *addr;
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size_t size;
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if (pcm_play_dma_complete_callback((res & 0x70) ?
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PCM_DMAST_ERR_DMA : PCM_DMAST_OK,
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&addr, &size))
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{
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SAR0 = (unsigned long)addr; /* Source address */
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BCR0 = (unsigned long)size; /* Bytes to transfer */
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or_l(DMA_EEXT | DMA_INT, &DCR0); /* per request and int ON */
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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/* else inished playing */
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} /* DMA0 */
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#ifdef HAVE_RECORDING
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/****************************************************************************
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** Recording DMA transfer
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**/
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static struct dma_lock dma_rec_lock =
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{
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.locked = 0,
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.state = (1 << 15) /* bit 15 is DMA1 */
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};
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/* For the locks, DMA interrupt must be disabled when manipulating the lock
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if the handler ever calls these - right now things are arranged so it
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doesn't */
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void pcm_rec_lock(void)
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{
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if (++dma_rec_lock.locked == 1)
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coldfire_imr_mod(1 << 15, 1 << 15);
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}
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void pcm_rec_unlock(void)
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{
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if (--dma_rec_lock.locked == 0)
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coldfire_imr_mod(dma_rec_lock.state, 1 << 15);
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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/* Stop any DMA in progress */
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pcm_rec_dma_stop();
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and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
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/* Start the DMA transfer.. */
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#ifdef HAVE_SPDIF_REC
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/* clear: ebu1cnew, valnogood, symbolerr, parityerr */
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INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
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#endif
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SAR1 = (unsigned long)&PDIR2; /* Source address */
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DAR1 = (unsigned long)addr; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
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DMA_DSIZE(DMA_SIZE_LINE) | DMA_START;
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dma_rec_lock.state = (0 << 15);
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} /* pcm_rec_dma_start */
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void pcm_rec_dma_stop(void)
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{
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and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
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DSR1 = 1; /* Clear interrupt, errors, stop transfer */
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BCR1 = 0; /* No bytes received */
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or_l(PDIR2_FIFO_RESET, &DATAINCONTROL);
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iis_play_reset_if_playback(false);
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dma_rec_lock.state = (1 << 15);
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} /* pcm_rec_dma_stop */
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void pcm_rec_dma_init(void)
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{
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DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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and_l(0xffff00ff, &DMAROUTE);
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or_l(DMA1_REQ_AUDIO_2, &DMAROUTE);
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pcm_rec_dma_stop();
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/* Enable interrupt at level 6, priority 1 */
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ICR7 = (6 << 2) | (1 << 0);
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} /* pcm_init_recording */
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void pcm_rec_dma_close(void)
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{
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pcm_rec_dma_stop();
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and_l(0xffff00ff, &DMAROUTE);
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ICR7 = 0x00; /* Disable interrupt */
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dma_rec_lock.state = (0 << 15);
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} /* pcm_rec_dma_close */
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/* DMA1 Interrupt is called when the DMA has finished transfering a chunk
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into the caller's buffer */
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void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA1(void)
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{
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unsigned long res = DSR1;
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enum pcm_dma_status status = PCM_DMAST_OK;
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and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
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DSR1 = 1; /* Clear interrupt and errors */
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if (res & 0x70)
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{
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status = PCM_DMAST_ERR_DMA;
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logf("DMA1 err: %02x", res);
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#if 0
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logf(" SAR1: %08x", SAR1);
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logf(" DAR1: %08x", DAR1);
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logf(" BCR1: %08x", BCR1);
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logf(" DCR1: %08x", DCR1);
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#endif
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}
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#ifdef HAVE_SPDIF_REC
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else if (DATAINCONTROL == 0xc038 &&
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(INTERRUPTSTAT & ((1 << 23) | (1 << 22))))
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{
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/* reason: symbolerr, parityerr.
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* Ignore valnogood since several sources don't set it properly. */
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/* clear: ebu1cnew, symbolerr, parityerr */
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INTERRUPTCLEAR = (1 << 25) | (1 << 23) | (1 << 22);
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status = PCM_DMAST_ERR_SPDIF;
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logf("spdif err");
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}
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#endif
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/* Inform PCM we have more data (or error) */
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void *addr;
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size_t size;
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if (pcm_rec_dma_complete_callback(status, &addr, &size))
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{
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DAR1 = (unsigned long)addr; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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or_l(DMA_EEXT | DMA_INT, &DCR1); /* per request and int ON */
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pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
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}
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} /* DMA1 */
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const void * pcm_rec_dma_get_peak_buffer(void)
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{
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return (void *)(DAR1 & ~3);
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} /* pcm_rec_dma_get_peak_buffer */
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#endif
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