541 lines
16 KiB
C
541 lines
16 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "usb.h"
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#include "usb_drv.h"
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#include "usb_ch9.h"
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#include "usb_core.h"
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#include <inttypes.h>
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#include "power.h"
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#define LOGF_ENABLE
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#include "logf.h"
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typedef volatile uint32_t reg32;
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#ifdef LOGF_ENABLE
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#define XFER_DIR_STR(dir) ((dir) ? "IN" : "OUT")
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#define XFER_TYPE_STR(type) \
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((type) == USB_ENDPOINT_XFER_CONTROL ? "CTRL" : \
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((type) == USB_ENDPOINT_XFER_ISOC ? "ISOC" : \
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((type) == USB_ENDPOINT_XFER_BULK ? "BULK" : \
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((type) == USB_ENDPOINT_XFER_INT ? "INTR" : "INVL"))))
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#endif
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struct endpoint_t
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{
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const int ep_num; /* EP number */
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const int type; /* EP type */
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const int dir; /* DIR_IN/DIR_OUT */
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volatile unsigned long *stat; /* RXSTAT/TXSTAT register */
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bool allocated; /* flag to mark EPs taken */
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volatile void *buf; /* tx/rx buffer address */
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volatile int len; /* size of the transfer (bytes) */
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volatile int cnt; /* number of bytes transfered/received */
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volatile bool block; /* flag indicating that transfer is blocking */
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struct semaphore complete; /* semaphore for blocking transfers */
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};
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/* compute RXCON address from RXSTAT, and so on */
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#define RXSTAT(endp) *((endp)->stat)
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#define RXCON(endp) *(1 + (endp)->stat)
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#define DMAOUTCTL(endp) *(2 + (endp)->stat)
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#define DMAOUTLMADDR(endp) *(3 + (endp)->stat)
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/* compute TXCON address from TXSTAT, and so on */
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#define TXSTAT(endp) *((endp)->stat)
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#define TXCON(endp) *(1 + (endp)->stat)
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#define TXBUF(endp) *(2 + (endp)->stat)
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#define DMAINCTL(endp) *(3 + (endp)->stat)
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#define DMAINLMADDR(endp) *(4 + (endp)->stat)
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#define ENDPOINT(num, type, dir, reg) \
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{num, USB_ENDPOINT_XFER_##type, USB_DIR_##dir, reg, false, NULL, 0, 0, true, {{0, 0}, 0, 0}}
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static struct endpoint_t ctrlep[2] =
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{
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ENDPOINT(0, CONTROL, OUT, &RX0STAT),
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ENDPOINT(0, CONTROL, IN, &TX0STAT),
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};
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static struct endpoint_t endpoints[16] =
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{
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ENDPOINT(0, CONTROL, OUT, NULL), /* stub */
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ENDPOINT(1, BULK, OUT, &RX1STAT), /* BOUT1 */
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ENDPOINT(2, BULK, IN, &TX2STAT), /* BIN2 */
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ENDPOINT(3, INT, IN, &TX3STAT), /* IIN3 */
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ENDPOINT(4, BULK, OUT, &RX4STAT), /* BOUT4 */
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ENDPOINT(5, BULK, IN, &TX5STAT), /* BIN5 */
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ENDPOINT(6, INT, IN, &TX6STAT), /* IIN6 */
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ENDPOINT(7, BULK, OUT, &RX7STAT), /* BOUT7 */
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ENDPOINT(8, BULK, IN, &TX8STAT), /* BIN8 */
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ENDPOINT(9, INT, IN, &TX9STAT), /* IIN9 */
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ENDPOINT(10, BULK, OUT, &RX10STAT), /* BOUT10 */
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ENDPOINT(11, BULK, IN, &TX11STAT), /* BIN11 */
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ENDPOINT(12, INT, IN, &TX12STAT), /* IIN12 */
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ENDPOINT(13, BULK, OUT, &RX13STAT), /* BOUT13 */
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ENDPOINT(14, BULK, IN, &TX14STAT), /* BIN14 */
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ENDPOINT(15, INT, IN, &TX15STAT), /* IIN15 */
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};
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static volatile bool set_address = false;
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static volatile bool set_configuration = false;
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#undef ENDPOINT
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static void setup_received(void)
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{
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static uint32_t setup_data[2];
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logf("udc: setup");
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/* copy setup data from packet */
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setup_data[0] = SETUP1;
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setup_data[1] = SETUP2;
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/* pass setup data to the upper layer */
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usb_core_legacy_control_request((struct usb_ctrlrequest*)setup_data);
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}
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static int max_pkt_size(struct endpoint_t *endp)
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{
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switch(endp->type)
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{
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case USB_ENDPOINT_XFER_CONTROL: return 64;
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case USB_ENDPOINT_XFER_BULK: return usb_drv_port_speed() ? 512 : 64;
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case USB_ENDPOINT_XFER_INT: return usb_drv_port_speed() ? 1024 : 64;
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default: panicf("die"); return 0;
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}
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}
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static void ep_write(struct endpoint_t *endp)
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{
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int xfer_size = MIN(max_pkt_size(endp), endp->cnt);
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unsigned int timeout = current_tick + HZ/10;
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while(TXBUF(endp) & TXFULL) /* TXFULL flag */
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{
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if(TIME_AFTER(current_tick, timeout))
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break;
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}
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/* setup transfer size and DMA */
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TXSTAT(endp) = xfer_size;
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DMAINLMADDR(endp) = (uint32_t)endp->buf; /* local buffer address */
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DMAINCTL(endp) = DMA_START;
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/* Decrement by max packet size is intentional.
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* This way if we have final packet short one we will get negative len
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* after transfer, which in turn indicates we *don't* need to send
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* zero length packet. If the final packet is max sized packet we will
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* get zero len after transfer which indicates we need to send
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* zero length packet to signal host end of the transfer.
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*/
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endp->cnt -= max_pkt_size(endp);
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endp->buf += xfer_size;
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/* clear NAK */
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TXCON(endp) &= ~TXNAK;
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}
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static void ep_read(struct endpoint_t *endp)
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{
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/* setup DMA */
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DMAOUTLMADDR(endp) = (uint32_t)endp->buf; /* local buffer address */
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DMAOUTCTL(endp) = DMA_START;
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/* clear NAK */
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RXCON(endp) &= ~RXNAK;
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}
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static void in_intr(struct endpoint_t *endp)
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{
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uint32_t txstat = TXSTAT(endp);
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/* check if clear feature was sent by host */
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if(txstat & TXCFINT)
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{
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logf("clear_stall: %d", endp->ep_num);
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usb_drv_stall(endp->ep_num, false, true);
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}
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/* check if a transfer has finished */
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if(txstat & TXACK)
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{
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logf("udc: ack(%d)", endp->ep_num);
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/* finished ? */
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if(endp->cnt <= 0)
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{
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usb_core_transfer_complete(endp->ep_num, endp->dir, 0, endp->len);
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/* release semaphore for blocking transfer */
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if(endp->block)
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semaphore_release(&endp->complete);
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}
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else /* more data to send */
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ep_write(endp);
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}
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}
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static void out_intr(struct endpoint_t *endp)
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{
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uint32_t rxstat = RXSTAT(endp);
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logf("udc: out intr(%d)", endp->ep_num);
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/* check if clear feature was sent by host */
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if(rxstat & RXCFINT)
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{
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logf("clear_stall: %d", endp->ep_num);
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usb_drv_stall(endp->ep_num, false, false);
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}
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/* check if a transfer has finished */
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if(rxstat & RXACK)
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{
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int xfer_size = rxstat & 0xffff;
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endp->cnt -= xfer_size;
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endp->buf += xfer_size;
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logf("udc: ack(%d) -> %d/%d", endp->ep_num, xfer_size, endp->cnt);
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/* finished ? */
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if(endp->cnt <= 0 || xfer_size < max_pkt_size(endp))
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usb_core_transfer_complete(endp->ep_num, endp->dir, 0, endp->len);
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else
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ep_read(endp);
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}
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}
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static void udc_phy_reset(void)
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{
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DEV_CTL |= SOFT_POR;
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udelay(10000); /* min 10ms */
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DEV_CTL &= ~SOFT_POR;
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}
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static void udc_soft_connect(void)
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{
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DEV_CTL |= CSR_DONE |
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DEV_SOFT_CN |
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DEV_SELF_PWR;
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}
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static void udc_helper(void)
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{
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uint32_t dev_info = DEV_INFO;
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/* This polls for DEV_EN bit set in DEV_INFO register
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* as well as tracks current requested configuration
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* (DEV_INFO [11:8]). On state change it notifies usb stack
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* about it.
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*/
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/* SET ADDRESS request */
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if(!set_address)
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if(dev_info & 0x7f)
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{
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set_address = true;
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usb_core_notify_set_address(dev_info & 0x7f);
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}
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/* SET CONFIGURATION request */
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if(!set_configuration)
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if(dev_info & DEV_EN)
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{
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set_configuration = true;
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usb_core_notify_set_config(((dev_info >> 7) & 0xf) + 1);
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}
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}
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/* return port speed FS=0, HS=1 */
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int usb_drv_port_speed(void)
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{
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return (DEV_INFO & DEV_SPEED) ? 0 : 1;
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}
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/* Reserve endpoint */
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int usb_drv_request_endpoint(int type, int dir)
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{
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logf("req: %s %s", XFER_DIR_STR(dir), XFER_TYPE_STR(type));
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/* Find an available ep/dir pair */
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for(int ep_num = 1; ep_num<USB_NUM_ENDPOINTS;ep_num++)
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{
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struct endpoint_t *endp = &endpoints[ep_num];
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if(endp->allocated || endp->type != type || endp->dir != dir)
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continue;
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/* allocate endpoint and enable interrupt */
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endp->allocated = true;
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if(dir == USB_DIR_IN)
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TXCON(endp) = (ep_num << 8) | TXEPEN | TXNAK | TXACKINTEN | TXCFINTE;
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else
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RXCON(endp) = (ep_num << 8) | RXEPEN | RXNAK | RXACKINTEN | RXCFINTE | RXERRINTEN;
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EN_INT |= 1 << (ep_num + 7);
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logf("add: ep%d %s", ep_num, XFER_DIR_STR(dir));
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return ep_num | dir;
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}
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return -1;
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}
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/* Free endpoint */
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void usb_drv_release_endpoint(int ep)
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{
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int ep_num = EP_NUM(ep);
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logf("rel: ep%d", ep_num);
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endpoints[ep_num].allocated = false;
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/* disable interrupt from this endpoint */
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EN_INT &= ~(1 << (ep_num + 7));
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}
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/* Set the address (usually it's in a register).
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* There is a problem here: some controller want the address to be set between
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* control out and ack and some want to wait for the end of the transaction.
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* In the first case, you need to write some code special code when getting
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* setup packets and ignore this function (have a look at other drives)
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*/
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void usb_drv_set_address(int address)
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{
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(void)address;
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/* UDC seems to set this automaticaly */
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}
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static int _usb_drv_send(int endpoint, void *ptr, int length, bool block)
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{
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logf("udc: send(%x)", endpoint);
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struct endpoint_t *ep;
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int ep_num = EP_NUM(endpoint);
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if (ep_num == 0)
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ep = &ctrlep[DIR_IN];
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else
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ep = &endpoints[ep_num];
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/* for send transfers, make sure the data is committed */
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commit_discard_dcache_range(ptr, length);
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ep->buf = ptr;
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ep->len = ep->cnt = length;
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ep->block = block;
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ep_write(ep);
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/* wait for transfer to end */
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if(block)
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semaphore_wait(&ep->complete, TIMEOUT_BLOCK);
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return 0;
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}
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/* Setup a send transfer. (blocking) */
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int usb_drv_send(int endpoint, void *ptr, int length)
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{
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return _usb_drv_send(endpoint, ptr, length, true);
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}
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/* Setup a send transfer. (non blocking) */
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int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
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{
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return _usb_drv_send(endpoint, ptr, length, false);
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}
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/* Setup a receive transfer. (non blocking) */
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int usb_drv_recv_nonblocking(int endpoint, void* ptr, int length)
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{
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logf("udc: recv(%x)", endpoint);
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struct endpoint_t *ep;
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int ep_num = EP_NUM(endpoint);
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if(ep_num == 0)
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ep = &ctrlep[DIR_OUT];
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else
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ep = &endpoints[ep_num];
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/* for recv, discard the cache lines related to the buffer */
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commit_discard_dcache_range(ptr, length);
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ep->buf = ptr;
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ep->len = ep->cnt = length;
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ep_read(ep);
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return 0;
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}
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/* Kill all transfers. Usually you need to set a bit for each endpoint
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* and flush fifos. You should also call the completion handler with
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* error status for everything
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*/
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void usb_drv_cancel_all_transfers(void)
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{
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}
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/* Set test mode, you can forget that for now, usually it's sufficient
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* to bit copy the argument into some register of the controller
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*/
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void usb_drv_set_test_mode(int mode)
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{
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(void)mode;
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}
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/* Check if endpoint is in stall state */
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bool usb_drv_stalled(int endpoint, bool in)
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{
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struct endpoint_t *endp = &endpoints[EP_NUM(endpoint)];
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if(in)
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return !!(TXCON(endp) & TXSTALL);
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else
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return !!(RXCON(endp) & RXSTALL);
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}
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/* Stall the endpoint. Usually set a flag in the controller */
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void usb_drv_stall(int endpoint, bool stall, bool in)
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{
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struct endpoint_t *endp = &endpoints[EP_NUM(endpoint)];
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if(in)
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{
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if(stall)
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TXCON(endp) |= TXSTALL;
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else
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TXCON(endp) &= ~TXSTALL;
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}
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else
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{
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if(stall)
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RXCON(endp) |= RXSTALL;
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else
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RXCON(endp) &= ~RXSTALL;
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}
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}
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/* one time init (once per connection) - basicaly enable usb core */
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void usb_drv_init(void)
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{
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/* init semaphore of ep0 */
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semaphore_init(&ctrlep[DIR_OUT].complete, 1, 0);
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semaphore_init(&ctrlep[DIR_IN].complete, 1, 0);
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for(int ep_num = 1; ep_num < USB_NUM_ENDPOINTS; ep_num++)
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semaphore_init(&endpoints[ep_num].complete, 1, 0);
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}
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/* turn off usb core */
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void usb_drv_exit(void)
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{
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DEV_CTL = DEV_SELF_PWR;
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/* disable USB interrupts in interrupt controller */
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INTC_IMR &= ~IRQ_ARM_UDC;
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INTC_IECR &= ~IRQ_ARM_UDC;
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/* we cannot disable UDC clock since this causes data abort
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* when reading DEV_INFO in order to check usb connect event
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*/
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}
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int usb_detect(void)
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{
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if(DEV_INFO & VBUS_STS)
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return USB_INSERTED;
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else
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return USB_EXTRACTED;
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}
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/* UDC ISR function */
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void INT_UDC(void)
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{
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/* read what caused UDC irq */
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uint32_t intsrc = INT2FLAG & 0x7fffff;
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if(intsrc & USBRST_INTR) /* usb reset */
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{
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logf("udc_int: reset, %ld", current_tick);
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EN_INT = EN_SUSP_INTR | /* Enable Suspend Irq */
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EN_RESUME_INTR | /* Enable Resume Irq */
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EN_USBRST_INTR | /* Enable USB Reset Irq */
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EN_OUT0_INTR | /* Enable OUT Token receive Irq EP0 */
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EN_IN0_INTR | /* Enable IN Token transmit Irq EP0 */
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EN_SETUP_INTR; /* Enable SETUP Packet Receive Irq */
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INTCON = UDC_INTHIGH_ACT | /* interrupt high active */
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UDC_INTEN; /* enable EP0 irqs */
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TX0CON = TXACKINTEN | /* Set as one to enable the EP0 tx irq */
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TXNAK; /* Set as one to response NAK handshake */
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RX0CON = RXACKINTEN |
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RXEPEN | /* Endpoint 0 Enable. When cleared the
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* endpoint does not respond to an SETUP
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* or OUT token */
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RXNAK; /* Set as one to response NAK handshake */
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set_address = false;
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set_configuration = false;
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}
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/* This needs to be processed AFTER usb reset */
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udc_helper();
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if(intsrc & SETUP_INTR) /* setup interrupt */
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{
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setup_received();
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}
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if(intsrc & IN0_INTR)
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{
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/* EP0 IN done */
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in_intr(&ctrlep[DIR_IN]);
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}
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if(intsrc & OUT0_INTR)
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|
{
|
|
/* EP0 OUT done */
|
|
out_intr(&ctrlep[DIR_OUT]);
|
|
}
|
|
if(intsrc & USBRST_INTR)
|
|
{
|
|
/* usb reset */
|
|
usb_drv_init();
|
|
}
|
|
if(intsrc & RESUME_INTR)
|
|
{
|
|
/* usb resume */
|
|
TX0CON |= TXCLR; /* TxClr */
|
|
TX0CON &= ~TXCLR;
|
|
RX0CON |= RXCLR; /* RxClr */
|
|
RX0CON &= ~RXCLR;
|
|
}
|
|
if(intsrc & SUSP_INTR)
|
|
{
|
|
/* usb suspend */
|
|
}
|
|
if(intsrc & CONN_INTR)
|
|
{
|
|
/* usb connect */
|
|
udc_phy_reset();
|
|
udelay(10000); /* wait at least 10ms */
|
|
udc_soft_connect();
|
|
}
|
|
/* other endpoints */
|
|
for(int ep_num = 1; ep_num < 16; ep_num++)
|
|
{
|
|
if(!(intsrc & (1 << (ep_num + 7))))
|
|
continue;
|
|
struct endpoint_t *endp = &endpoints[ep_num];
|
|
if(endp->dir == USB_DIR_IN)
|
|
in_intr(endp);
|
|
else
|
|
out_intr(endp);
|
|
}
|
|
}
|