1676 lines
47 KiB
C
1676 lines
47 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009-2014 by Michael Sparmann
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* Copyright © 2010 Amaury Pouly
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* Copyright (C) 2014 by Marcin Bukat
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* Copyright (C) 2016 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <inttypes.h>
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#include <string.h>
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#include "config.h"
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#include "power.h"
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#include "usb.h"
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#include "usb_drv.h"
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#include "usb_ch9.h"
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#include "usb_core.h"
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#include "usb-designware.h"
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/* Define LOGF_ENABLE to enable logf output in this file */
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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/* The ARM940T uses a subset of the ARMv4 functions, not
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* supporting clean/invalidate cache entries using MVA.
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*/
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#if CONFIG_CPU == S5L8701
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#define DISCARD_DCACHE_RANGE(b,s) commit_discard_dcache()
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#define COMMIT_DCACHE_RANGE(b,s) commit_dcache()
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#else
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#define DISCARD_DCACHE_RANGE(b,s) discard_dcache_range(b,s)
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#define COMMIT_DCACHE_RANGE(b,s) commit_dcache_range(b,s)
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#endif
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/* USB_DW_PHYSADDR(x) converts the address of buffer x to one usable with DMA.
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* For example, converting a virtual address to a physical address.
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*
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* USB_DW_UNCACHEDADDR(x) is used to get an uncached pointer to a buffer.
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* If the platform doesn't support this, define NO_UNCACHED_ADDR instead.
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*
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* Define POST_DMA_FLUSH if the driver should discard DMA RX buffers after a
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* transfer completes. Needed if the CPU can speculatively fetch cache lines
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* in any way, eg. due to speculative execution / prefetching.
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*/
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#if CONFIG_CPU == X1000
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# define USB_DW_PHYSADDR(x) PHYSADDR(x)
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# define USB_DW_UNCACHEDADDR(x) ((typeof(x))UNCACHEDADDR(x))
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# define POST_DMA_FLUSH
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#elif CONFIG_CPU == AS3525v2
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# define USB_DW_PHYSADDR(x) AS3525_PHYSICAL_ADDR(x)
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# define USB_DW_UNCACHEDADDR(x) AS3525_UNCACHED_ADDR(x)
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#elif CONFIG_CPU == S5L8701
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# define USB_DW_PHYSADDR(x) x
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# define NO_UNCACHED_ADDR /* Not known how to form uncached addresses */
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#elif CONFIG_CPU == S5L8702
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# define USB_DW_PHYSADDR(x) S5L8702_PHYSICAL_ADDR(x)
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# define USB_DW_UNCACHEDADDR(x) S5L8702_UNCACHED_ADDR(x)
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#elif !defined(USB_DW_ARCH_SLAVE)
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# error "Must define USB_DW_PHYSADDR / USB_DW_UNCACHEDADDR!"
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#endif
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#ifndef USB_DW_TOUTCAL
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#define USB_DW_TOUTCAL 0
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#endif
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#define GET_DTXFNUM(ep) ((DWC_DIEPCTL(ep)>>22) & 0xf)
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#define USB_DW_NUM_DIRS 2
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#define USB_DW_DIR_OFF(dir) (((dir) == USB_DW_EPDIR_IN) ? 0 : 16)
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enum usb_dw_epdir
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{
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USB_DW_EPDIR_IN = 0,
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USB_DW_EPDIR_OUT = 1,
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};
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enum usb_dw_ep0_state
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{
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/* Waiting for a setup packet to arrive. This is the default state. */
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EP0_SETUP,
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/* Request wait states -- after submitting a request, we enter EP0_REQ
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* (or EP0_REQ_CTRLWRITE for control writes). EP0_REQ is also used for
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* the 2nd phase of a control write. EP0_REQ_CANCELLED is entered if we
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* receive a setup packet before getting a response from the USB stack. */
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EP0_REQ,
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EP0_REQ_CTRLWRITE,
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EP0_REQ_CANCELLED,
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/* Waiting for a data phase to complete. */
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EP0_DATA_IN,
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EP0_DATA_OUT,
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/* Waiting for the status phase */
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EP0_STATUS_IN,
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EP0_STATUS_OUT,
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EP0_NUM_STATES
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};
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/* Internal EP state/info */
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struct usb_dw_ep
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{
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struct semaphore complete;
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void* req_addr;
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uint32_t req_size;
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uint32_t* addr;
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uint32_t sizeleft;
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uint32_t size;
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int8_t status;
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uint8_t active;
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uint8_t busy;
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};
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/* Additional state for EP0 */
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struct usb_dw_ep0
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{
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enum usb_dw_ep0_state state;
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struct usb_ctrlrequest active_req;
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struct usb_ctrlrequest pending_req;
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};
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static const char* const dw_dir_str[USB_DW_NUM_DIRS] =
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{
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[USB_DW_EPDIR_IN] = "IN",
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[USB_DW_EPDIR_OUT] = "OUT",
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};
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static const char* const dw_state_str[EP0_NUM_STATES] =
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{
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[EP0_SETUP] = "setup",
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[EP0_REQ] = "req",
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[EP0_REQ_CTRLWRITE] = "req_cw",
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[EP0_DATA_IN] = "dat_in",
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[EP0_DATA_OUT] = "dat_out",
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[EP0_STATUS_IN] = "sts_in",
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[EP0_STATUS_OUT] = "sts_out",
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};
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static const char* const dw_resp_str[3] =
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{
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[USB_CONTROL_ACK] = "ACK",
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[USB_CONTROL_RECEIVE] = "RECV",
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[USB_CONTROL_STALL] = "STALL",
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};
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static struct usb_dw_ep usb_dw_ep_list[USB_NUM_ENDPOINTS][USB_DW_NUM_DIRS];
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static struct usb_dw_ep0 ep0;
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uint8_t _ep0_buffer[64] USB_DEVBSS_ATTR __attribute__((aligned(32)));
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uint8_t* ep0_buffer; /* Uncached, unless NO_UNCACHED_ADDR is defined */
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static uint32_t usb_endpoints; /* available EPs mask */
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/* For SHARED_FIFO mode this is the number of periodic Tx FIFOs
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(usually 1), otherwise it is the number of dedicated Tx FIFOs
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(not counting NPTX FIFO that is always dedicated for IN0). */
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static int n_ptxfifos;
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static uint16_t ptxfifo_usage;
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static uint32_t hw_maxbytes;
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static uint32_t hw_maxpackets;
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#ifdef USB_DW_SHARED_FIFO
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static uint8_t hw_nptxqdepth;
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static uint32_t epmis_msk;
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static uint32_t ep_periodic_msk;
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#endif
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static struct usb_dw_ep *usb_dw_get_ep(int epnum, enum usb_dw_epdir epdir)
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{
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return &usb_dw_ep_list[epnum][epdir];
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}
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static uint32_t usb_dw_maxpktsize(int epnum, enum usb_dw_epdir epdir)
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{
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return epnum ? DWC_EPCTL(epnum, epdir) & 0x3ff : 64;
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}
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static uint32_t usb_dw_maxxfersize(int epnum, enum usb_dw_epdir epdir)
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{
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/* EP0 can only transfer one packet at a time. */
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if(epnum == 0)
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return 64;
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uint32_t maxpktsize = usb_dw_maxpktsize(epnum, epdir);
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return CACHEALIGN_DOWN(MIN(hw_maxbytes, hw_maxpackets * maxpktsize));
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}
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/* Calculate number of packets (if size == 0 an empty packet will be sent) */
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static uint32_t usb_dw_calc_packets(uint32_t size, uint32_t maxpktsize)
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{
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return MAX(1, (size + maxpktsize - 1) / maxpktsize);
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}
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static int usb_dw_get_stall(int epnum, enum usb_dw_epdir epdir)
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{
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return !!(DWC_EPCTL(epnum, epdir) & STALL);
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}
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static void usb_dw_set_stall(int epnum, enum usb_dw_epdir epdir, int stall)
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{
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if (stall)
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{
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DWC_EPCTL(epnum, epdir) |= STALL;
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}
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else
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{
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DWC_EPCTL(epnum, epdir) &= ~STALL;
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DWC_EPCTL(epnum, epdir) |= SD0PID;
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}
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}
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static void usb_dw_set_address(uint8_t address)
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{
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DWC_DCFG = (DWC_DCFG & ~(0x7f0)) | DAD(address);
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}
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static void usb_dw_wait_for_ahb_idle(void)
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{
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while (!(DWC_GRSTCTL & AHBIDL));
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}
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#ifdef USB_DW_SHARED_FIFO
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static unsigned usb_dw_bytes_in_txfifo(int epnum, uint32_t *sentbytes)
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{
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uint32_t size = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN)->size;
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if (sentbytes) *sentbytes = size;
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uint32_t dieptsiz = DWC_DIEPTSIZ(epnum);
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uint32_t packetsleft = (dieptsiz >> 19) & 0x3ff;
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if (!packetsleft) return 0;
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uint32_t maxpktsize = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN);
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uint32_t packets = usb_dw_calc_packets(size, maxpktsize);
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uint32_t bytesleft = dieptsiz & 0x7ffff;
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uint32_t bytespushed = size - bytesleft;
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uint32_t bytespulled = (packets - packetsleft) * maxpktsize;
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if (sentbytes) *sentbytes = bytespulled;
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return bytespushed - bytespulled;
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}
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#endif
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#ifdef USB_DW_ARCH_SLAVE
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/* Read one packet/token from Rx FIFO */
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static void usb_dw_handle_rxfifo(void)
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{
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uint32_t rxsts = DWC_GRXSTSP;
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uint32_t pktsts = (rxsts >> 17) & 0xf;
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switch (pktsts)
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{
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case PKTSTS_OUTRX:
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case PKTSTS_SETUPRX:
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{
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int ep = rxsts & 0xf;
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uint32_t words = (((rxsts >> 4) & 0x7ff) + 3) >> 2;
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/* Annoyingly, we need to special-case EP0. */
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if(ep == 0)
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{
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uint32_t* addr = (uint32_t*)ep0_buffer;
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while (words--)
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*addr++ = DWC_DFIFO(0);
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}
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else
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{
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, USB_DW_EPDIR_OUT);
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if (dw_ep->busy)
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{
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while (words--)
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*dw_ep->addr++ = DWC_DFIFO(0);
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}
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else
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{
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/* Discard data */
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while (words--)
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(void) DWC_DFIFO(0);
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}
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}
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break;
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}
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case PKTSTS_OUTDONE:
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case PKTSTS_SETUPDONE:
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case PKTSTS_GLOBALOUTNAK:
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default:
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break;
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}
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}
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#ifdef USB_DW_SHARED_FIFO
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static void usb_dw_try_push(int epnum)
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{
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
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if (!dw_ep->busy)
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return;
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if (epmis_msk & (1 << epnum))
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return;
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uint32_t wordsleft = ((DWC_DIEPTSIZ(epnum) & 0x7ffff) + 3) >> 2;
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if (!wordsleft) return;
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/* Get fifo space for NPTXFIFO or PTXFIFO */
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uint32_t fifospace;
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int dtxfnum = GET_DTXFNUM(epnum);
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if (dtxfnum)
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{
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uint32_t fifosize = DWC_DIEPTXF(dtxfnum - 1) >> 16;
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fifospace = fifosize - ((usb_dw_bytes_in_txfifo(epnum, NULL) + 3) >> 2);
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}
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else
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{
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uint32_t gnptxsts = DWC_GNPTXSTS;
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fifospace = ((gnptxsts >> 16) & 0xff) ? (gnptxsts & 0xffff) : 0;
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}
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uint32_t maxpktsize = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN);
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uint32_t words = MIN((maxpktsize + 3) >> 2, wordsleft);
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if (fifospace >= words)
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{
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wordsleft -= words;
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while (words--)
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DWC_DFIFO(epnum) = *dw_ep->addr++;
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}
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if (wordsleft)
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DWC_GINTMSK |= (dtxfnum ? PTXFE : NPTXFE);
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}
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#else /* !USB_DW_SHARED_FIFO */
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static void usb_dw_handle_dtxfifo(int epnum)
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{
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
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if (!dw_ep->busy)
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return;
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uint32_t wordsleft = ((DWC_DIEPTSIZ(epnum) & 0x7ffff) + 3) >> 2;
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while (wordsleft)
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{
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uint32_t words = wordsleft;
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uint32_t fifospace = DWC_DTXFSTS(epnum) & 0xffff;
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if (fifospace < words)
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{
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/* We push whole packets to read consistent info on DIEPTSIZ
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(i.e. when FIFO size is not maxpktsize multiplo). */
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uint32_t maxpktwords = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN) >> 2;
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words = (fifospace / maxpktwords) * maxpktwords;
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}
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if (!words)
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break;
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wordsleft -= words;
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while (words--)
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DWC_DFIFO(epnum) = *dw_ep->addr++;
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}
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if (!wordsleft)
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DWC_DIEPEMPMSK &= ~(1 << GET_DTXFNUM(epnum));
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}
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#endif /* !USB_DW_SHARED_FIFO */
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#endif /* USB_DW_ARCH_SLAVE */
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static void usb_dw_flush_fifo(uint32_t fflsh, int fnum)
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{
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#ifdef USB_DW_ARCH_SLAVE
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/* Rx queue must be emptied before flushing Rx FIFO */
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if (fflsh & RXFFLSH)
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while (DWC_GINTSTS & RXFLVL)
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usb_dw_handle_rxfifo();
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#else
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/* Wait for any DMA activity to stop */
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usb_dw_wait_for_ahb_idle();
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#endif
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DWC_GRSTCTL = TXFNUM(fnum) | fflsh;
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while (DWC_GRSTCTL & fflsh);
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udelay(1); /* Wait 3 PHY cycles */
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}
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/* These are the conditions that must be met so that the application can
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* disable an endpoint avoiding race conditions:
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*
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* 1) The endpoint must be enabled when EPDIS is written, otherwise the
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* core will never raise EPDISD interrupt (thus EPDIS remains enabled).
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*
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* 2) - Periodic (SHARED_FIFO) or dedicated (!SHARED_FIFO) IN endpoints:
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* IN NAK must be effective, to ensure that the core is not going
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* to disable the EP just before EPDIS is written.
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* - Non-periodic (SHARED_FIFO) IN endpoints: use usb_dw_nptx_unqueue().
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* - OUT endpoints: GONAK must be effective, this also ensures that the
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* core is not going to disable the EP.
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*/
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static void usb_dw_disable_ep(int epnum, enum usb_dw_epdir epdir)
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{
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if (!epnum && (epdir == USB_DW_EPDIR_OUT))
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return; /* The application cannot disable OUT0 */
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if (DWC_EPCTL(epnum, epdir) & EPENA)
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{
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int tmo = 50;
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DWC_EPCTL(epnum, epdir) |= EPDIS;
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while (DWC_EPCTL(epnum, epdir) & EPDIS)
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{
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if (!tmo--)
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panicf("%s: %s%d failed!", __func__, dw_dir_str[epdir], epnum);
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udelay(1);
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}
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}
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}
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|
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static void usb_dw_gonak_effective(bool enable)
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{
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if (enable)
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{
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if (!(DWC_DCTL & GONSTS))
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DWC_DCTL |= SGONAK;
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|
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/* Wait for global IN NAK effective */
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int tmo = 50;
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while (~DWC_GINTSTS & GOUTNAKEFF)
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{
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if (!tmo--) panicf("%s: failed!", __func__);
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#ifdef USB_DW_ARCH_SLAVE
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/* Pull Rx queue until GLOBALOUTNAK token is received. */
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if (DWC_GINTSTS & RXFLVL)
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usb_dw_handle_rxfifo();
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else
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#endif
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udelay(1);
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}
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}
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else
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{
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if (DWC_DCTL & GONSTS)
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DWC_DCTL |= CGONAK;
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}
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}
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|
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static void usb_dw_set_innak_effective(int epnum)
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{
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if (~DWC_DIEPCTL(epnum) & NAKSTS)
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{
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/* Wait for IN NAK effective avoiding race conditions, if the
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* endpoint is disabled by the core (or it was already disabled)
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* then INEPNE is never raised.
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|
*/
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|
int tmo = 50;
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DWC_DIEPCTL(epnum) |= SNAK;
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while ((DWC_DIEPCTL(epnum) & EPENA) && !(DWC_DIEPINT(epnum) & INEPNE))
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{
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if (!tmo--) panicf("%s: IN%d failed!", __func__, epnum);
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udelay(1);
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|
}
|
|
}
|
|
}
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
static void usb_dw_ginak_effective(bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
if (!(DWC_DCTL & GINSTS))
|
|
DWC_DCTL |= SGINAK;
|
|
|
|
/* Wait for global IN NAK effective */
|
|
int tmo = 50;
|
|
while (~DWC_GINTSTS & GINAKEFF)
|
|
{
|
|
if (!tmo--) panicf("%s: failed!", __func__);
|
|
udelay(1);
|
|
}
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
/* Wait for any DMA activity to stop. */
|
|
usb_dw_wait_for_ahb_idle();
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
if (DWC_DCTL & GINSTS)
|
|
DWC_DCTL |= CGINAK;
|
|
}
|
|
}
|
|
|
|
static void usb_dw_nptx_unqueue(int epnum)
|
|
{
|
|
uint32_t reenable_msk = 0;
|
|
|
|
usb_dw_ginak_effective(true);
|
|
|
|
/* Disable EPs */
|
|
for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
{
|
|
if (usb_endpoints & ~ep_periodic_msk & (1 << ep))
|
|
{
|
|
/* Disable */
|
|
if (~DWC_DIEPCTL(ep) & EPENA)
|
|
continue;
|
|
DWC_DIEPCTL(ep) |= EPDIS|SNAK;
|
|
|
|
/* Adjust */
|
|
uint32_t packetsleft = (DWC_DIEPTSIZ(ep) >> 19) & 0x3ff;
|
|
if (!packetsleft) continue;
|
|
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, USB_DW_EPDIR_IN);
|
|
uint32_t sentbytes;
|
|
uint32_t bytesinfifo = usb_dw_bytes_in_txfifo(ep, &sentbytes);
|
|
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
dw_ep->addr -= (bytesinfifo + 3) >> 2;
|
|
#else
|
|
(void) bytesinfifo;
|
|
DWC_DIEPDMA(ep) = USB_DW_PHYSADDR((uint32_t)(dw_ep->addr) + sentbytes);
|
|
#endif
|
|
DWC_DIEPTSIZ(ep) = PKTCNT(packetsleft) | (dw_ep->size - sentbytes);
|
|
|
|
/* Do not re-enable the EP we are going to unqueue */
|
|
if (ep == epnum)
|
|
continue;
|
|
|
|
/* Mark EP to be re-enabled later */
|
|
reenable_msk |= (1 << ep);
|
|
}
|
|
}
|
|
|
|
/* Flush NPTXFIFO */
|
|
usb_dw_flush_fifo(TXFFLSH, 0);
|
|
|
|
/* Re-enable EPs */
|
|
for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
if (reenable_msk & (1 << ep))
|
|
DWC_DIEPCTL(ep) |= EPENA|CNAK;
|
|
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
if (reenable_msk)
|
|
DWC_GINTMSK |= NPTXFE;
|
|
#endif
|
|
|
|
usb_dw_ginak_effective(false);
|
|
}
|
|
#endif /* USB_DW_SHARED_FIFO */
|
|
|
|
static void usb_dw_flush_endpoint(int epnum, enum usb_dw_epdir epdir)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
|
|
dw_ep->busy = false;
|
|
dw_ep->status = -1;
|
|
semaphore_release(&dw_ep->complete);
|
|
|
|
if (DWC_EPCTL(epnum, epdir) & EPENA)
|
|
{
|
|
if (epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
/* We are shutting down an endpoint that might still have IN
|
|
* packets in the FIFO. Disable the endpoint, wait for things
|
|
* to settle, and flush the relevant FIFO.
|
|
*/
|
|
int dtxfnum = GET_DTXFNUM(epnum);
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if (!dtxfnum)
|
|
{
|
|
usb_dw_nptx_unqueue(epnum);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
/* Wait for IN NAK effective to avoid race conditions
|
|
while shutting down the endpoint. */
|
|
usb_dw_set_innak_effective(epnum);
|
|
|
|
/* Disable the EP we are going to flush */
|
|
usb_dw_disable_ep(epnum, epdir);
|
|
|
|
/* Flush it all the way down! */
|
|
usb_dw_flush_fifo(TXFFLSH, dtxfnum);
|
|
|
|
#if !defined(USB_DW_SHARED_FIFO) && defined(USB_DW_ARCH_SLAVE)
|
|
DWC_DIEPEMPMSK &= ~(1 << dtxfnum);
|
|
#endif
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* We are waiting for an OUT packet on this endpoint, which
|
|
* might arrive any moment. Assert a global output NAK to
|
|
* avoid race conditions while shutting down the endpoint.
|
|
* Global output NAK also flushes the Rx FIFO.
|
|
*/
|
|
usb_dw_gonak_effective(true);
|
|
usb_dw_disable_ep(epnum, epdir);
|
|
usb_dw_gonak_effective(false);
|
|
}
|
|
}
|
|
|
|
/* At this point the endpoint is disabled, SNAK it (in case it is not
|
|
* already done), it is needed for Tx shared FIFOs (to not to raise
|
|
* unwanted EPMIS interrupts) and recomended for dedicated FIFOs.
|
|
*/
|
|
DWC_EPCTL(epnum, epdir) |= SNAK;
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if (epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
epmis_msk &= ~(1 << epnum);
|
|
if (!epmis_msk)
|
|
DWC_DIEPMSK &= ~ITTXFE;
|
|
}
|
|
#endif
|
|
|
|
/* Clear all channel interrupts to avoid to process
|
|
pending tokens for the flushed EP. */
|
|
DWC_EPINT(epnum, epdir) = DWC_EPINT(epnum, epdir);
|
|
}
|
|
|
|
static void usb_dw_unconfigure_ep(int epnum, enum usb_dw_epdir epdir)
|
|
{
|
|
uint32_t epctl = 0;
|
|
|
|
if (epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
int next;
|
|
for (next = epnum + 1; next < USB_NUM_ENDPOINTS; next++)
|
|
if (usb_endpoints & (1 << next))
|
|
break;
|
|
epctl = NEXTEP(next % USB_NUM_ENDPOINTS);
|
|
#endif
|
|
ep_periodic_msk &= ~(1 << epnum);
|
|
#endif
|
|
ptxfifo_usage &= ~(1 << GET_DTXFNUM(epnum));
|
|
}
|
|
|
|
usb_dw_flush_endpoint(epnum, epdir);
|
|
DWC_EPCTL(epnum, epdir) = epctl;
|
|
}
|
|
|
|
static int usb_dw_configure_ep(int epnum,
|
|
enum usb_dw_epdir epdir, int type, int maxpktsize)
|
|
{
|
|
uint32_t epctl = SD0PID|EPTYP(type)|USBAEP|maxpktsize;
|
|
|
|
if (epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
/*
|
|
* If the hardware has dedicated fifos, we must give each
|
|
* IN EP a unique tx-fifo even if it is non-periodic.
|
|
*/
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
epctl |= DWC_DIEPCTL(epnum) & NEXTEP(0xf);
|
|
#endif
|
|
if (type == USB_ENDPOINT_XFER_INT)
|
|
#endif
|
|
{
|
|
int fnum;
|
|
for (fnum = 1; fnum <= n_ptxfifos; fnum++)
|
|
if (~ptxfifo_usage & (1 << fnum))
|
|
break;
|
|
if (fnum > n_ptxfifos)
|
|
return -1; /* no available fifos */
|
|
ptxfifo_usage |= (1 << fnum);
|
|
epctl |= DTXFNUM(fnum);
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
ep_periodic_msk |= (1 << epnum);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
DWC_EPCTL(epnum, epdir) = epctl;
|
|
return 0; /* ok */
|
|
}
|
|
|
|
static void usb_dw_reset_endpoints(void)
|
|
{
|
|
/* Initial state for all endpoints, setting OUT EPs as not busy
|
|
* will discard all pending data (if any) on the flush stage.
|
|
*/
|
|
for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
{
|
|
for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, dir);
|
|
dw_ep->active = !ep;
|
|
dw_ep->busy = false;
|
|
dw_ep->status = -1;
|
|
semaphore_release(&dw_ep->complete);
|
|
}
|
|
}
|
|
|
|
#if CONFIG_CPU == S5L8701
|
|
/*
|
|
* Workaround for spurious -EPROTO when receiving bulk data on Nano2G.
|
|
*
|
|
* The Rx FIFO and Rx queue are currupted by the received (corrupted)
|
|
* data, must be flushed, otherwise the core can not set GONAK effective.
|
|
*/
|
|
usb_dw_flush_fifo(RXFFLSH, 0);
|
|
#endif
|
|
|
|
/* Flush and initialize EPs, includes disabling USBAEP on all EPs
|
|
* except EP0 (USB HW core keeps EP0 active on all configurations).
|
|
*/
|
|
for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
{
|
|
if (usb_endpoints & (1 << (ep + 16)))
|
|
usb_dw_unconfigure_ep(ep, USB_DW_EPDIR_OUT);
|
|
if (usb_endpoints & (1 << ep))
|
|
usb_dw_unconfigure_ep(ep, USB_DW_EPDIR_IN);
|
|
}
|
|
|
|
ptxfifo_usage = 0;
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
ep_periodic_msk = 0;
|
|
#endif
|
|
}
|
|
|
|
static void usb_dw_epstart(int epnum, enum usb_dw_epdir epdir,
|
|
void* buf, uint32_t size)
|
|
{
|
|
if ((uint32_t)buf & ((epdir == USB_DW_EPDIR_IN) ? 3 : CACHEALIGN_SIZE-1))
|
|
logf("%s: %s%d %p unaligned", __func__, dw_dir_str[epdir], epnum, buf);
|
|
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
|
|
uint32_t xfersize = MIN(size, usb_dw_maxxfersize(epnum, epdir));
|
|
|
|
dw_ep->addr = (uint32_t*)buf;
|
|
dw_ep->size = xfersize;
|
|
dw_ep->sizeleft = size;
|
|
dw_ep->status = -1;
|
|
dw_ep->busy = true;
|
|
|
|
if (epnum == 0 && epdir == USB_DW_EPDIR_OUT)
|
|
{
|
|
/* FIXME: there's an extremely rare race condition here.
|
|
*
|
|
* 1. Host sends a control write.
|
|
* 2. We process the request.
|
|
* 3. (time passes)
|
|
* 4. This function is called via USB_CONTROL_RECEIVE response.
|
|
* 5. Right before we set CNAK, host sends another control write.
|
|
*
|
|
* So we may unintentionally receive data from the second request.
|
|
* It's possible to detect this when we see a setup packet because
|
|
* EP0 OUT will be busy. In principle it should even be possible to
|
|
* handle the 2nd request correctly. Currently we don't attempt to
|
|
* detect or recover from this error.
|
|
*/
|
|
DWC_DOEPCTL(0) |= CNAK;
|
|
return;
|
|
}
|
|
|
|
uint32_t maxpktsize = usb_dw_maxpktsize(epnum, epdir);
|
|
uint32_t packets = usb_dw_calc_packets(xfersize, maxpktsize);
|
|
uint32_t eptsiz = PKTCNT(packets) | xfersize;
|
|
uint32_t nak = CNAK;
|
|
|
|
if (epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
COMMIT_DCACHE_RANGE(buf, xfersize);
|
|
#endif
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
eptsiz |= MCCNT((ep_periodic_msk >> epnum) & 1);
|
|
#endif
|
|
|
|
}
|
|
else
|
|
{
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
DISCARD_DCACHE_RANGE(buf, xfersize);
|
|
#endif
|
|
}
|
|
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
DWC_EPDMA(epnum, epdir) = USB_DW_PHYSADDR((uint32_t)buf);
|
|
#endif
|
|
DWC_EPTSIZ(epnum, epdir) = eptsiz;
|
|
DWC_EPCTL(epnum, epdir) |= EPENA | nak;
|
|
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
/* Enable interrupts to start pushing data into the FIFO */
|
|
if ((epdir == USB_DW_EPDIR_IN) && dw_ep->size > 0)
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
DWC_GINTMSK |= ((ep_periodic_msk & (1 << epnum)) ? PTXFE : NPTXFE);
|
|
#else
|
|
DWC_DIEPEMPMSK |= (1 << GET_DTXFNUM(epnum));
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
static void usb_dw_transfer(int epnum, enum usb_dw_epdir epdir,
|
|
void* buf, uint32_t size)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
|
|
|
|
if (!dw_ep->active)
|
|
logf("%s: %s%d inactive", __func__, dw_dir_str[epdir], epnum);
|
|
if (dw_ep->busy)
|
|
logf("%s: %s%d busy", __func__, dw_dir_str[epdir], epnum);
|
|
|
|
dw_ep->req_addr = buf;
|
|
dw_ep->req_size = size;
|
|
usb_dw_epstart(epnum, epdir, buf, size);
|
|
}
|
|
|
|
static void usb_dw_ep0_recv(void)
|
|
{
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
#ifdef NO_UNCACHED_ADDR
|
|
DISCARD_DCACHE_RANGE(&_ep0_buffer[0], 64);
|
|
#endif
|
|
DWC_DOEPDMA(0) = USB_DW_PHYSADDR((uint32_t)&_ep0_buffer[0]);
|
|
#endif
|
|
DWC_DOEPTSIZ(0) = STUPCNT(1) | PKTCNT(1) | 64;
|
|
DWC_DOEPCTL(0) |= EPENA | SNAK;
|
|
}
|
|
|
|
static void usb_dw_abort_endpoint(int epnum, enum usb_dw_epdir epdir)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
|
|
if (dw_ep->busy)
|
|
{
|
|
usb_dw_flush_endpoint(epnum, epdir);
|
|
usb_core_transfer_complete(epnum, (epdir == USB_DW_EPDIR_OUT) ?
|
|
USB_DIR_OUT : USB_DIR_IN, -1, 0);
|
|
}
|
|
}
|
|
|
|
static void usb_dw_control_received(struct usb_ctrlrequest* req)
|
|
{
|
|
logf("%s(%p) state=%s", __func__, req, dw_state_str[ep0.state]);
|
|
logf(" bRequestType=%02x bRequest=%02x", req->bRequestType, req->bRequest);
|
|
logf(" wValue=%04x wIndex=%u wLength=%u", req->wValue, req->wIndex, req->wLength);
|
|
|
|
switch(ep0.state) {
|
|
case EP0_REQ:
|
|
case EP0_REQ_CTRLWRITE:
|
|
case EP0_REQ_CANCELLED:
|
|
/* Save the request for later */
|
|
memcpy(&ep0.pending_req, req, sizeof(*req));
|
|
ep0.state = EP0_REQ_CANCELLED;
|
|
break;
|
|
|
|
case EP0_DATA_IN:
|
|
case EP0_STATUS_IN:
|
|
case EP0_DATA_OUT:
|
|
case EP0_STATUS_OUT:
|
|
usb_core_control_complete(-1);
|
|
/* fallthrough */
|
|
|
|
case EP0_SETUP:
|
|
/* Save the request */
|
|
memcpy(&ep0.active_req, req, sizeof(*req));
|
|
req = &ep0.active_req;
|
|
|
|
/* Check for a SET ADDRESS request, which we must handle here */
|
|
if ((req->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE &&
|
|
(req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD &&
|
|
(req->bRequest == USB_REQ_SET_ADDRESS))
|
|
usb_dw_set_address(req->wValue);
|
|
|
|
/* Check for control writes */
|
|
if (req->wLength > 0 && !(req->bRequestType & USB_DIR_IN))
|
|
ep0.state = EP0_REQ_CTRLWRITE;
|
|
else
|
|
ep0.state = EP0_REQ;
|
|
|
|
usb_dw_flush_endpoint(0, USB_DW_EPDIR_IN);
|
|
usb_core_control_request(req, NULL);
|
|
break;
|
|
|
|
default:
|
|
panicf("%s: bad state=%s", __func__, ep0.state >= EP0_NUM_STATES ? "unk" : dw_state_str[ep0.state]);
|
|
}
|
|
}
|
|
|
|
/* note: must be called with IRQs disabled */
|
|
static void usb_dw_control_response(enum usb_control_response resp,
|
|
void* data, int length)
|
|
{
|
|
struct usb_ctrlrequest* req = &ep0.active_req;
|
|
|
|
switch(ep0.state) {
|
|
case EP0_REQ:
|
|
case EP0_REQ_CTRLWRITE:
|
|
switch(resp) {
|
|
case USB_CONTROL_ACK:
|
|
if(req->wLength > 0 && (req->bRequestType & USB_DIR_IN))
|
|
ep0.state = EP0_DATA_IN; /* control read */
|
|
else
|
|
ep0.state = EP0_STATUS_IN; /* non-data or write */
|
|
|
|
usb_dw_transfer(0, USB_DW_EPDIR_IN, data, length);
|
|
break;
|
|
|
|
case USB_CONTROL_RECEIVE:
|
|
if(ep0.state != EP0_REQ_CTRLWRITE)
|
|
panicf("%s: bad response", __func__);
|
|
|
|
ep0.state = EP0_DATA_OUT;
|
|
usb_dw_transfer(0, USB_DW_EPDIR_OUT, data, length);
|
|
break;
|
|
|
|
case USB_CONTROL_STALL:
|
|
if(ep0.state == EP0_REQ_CTRLWRITE)
|
|
usb_dw_set_stall(0, USB_DW_EPDIR_OUT, 1);
|
|
else
|
|
usb_dw_set_stall(0, USB_DW_EPDIR_IN, 1);
|
|
|
|
ep0.state = EP0_SETUP;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case EP0_REQ_CANCELLED:
|
|
/* Terminate the old request */
|
|
usb_core_control_complete(-3);
|
|
|
|
/* Submit the pending request */
|
|
ep0.state = EP0_SETUP;
|
|
usb_dw_control_received(&ep0.pending_req);
|
|
break;
|
|
|
|
default:
|
|
panicf("%s: bad state=%s", __func__, dw_state_str[ep0.state]);
|
|
}
|
|
}
|
|
|
|
static void usb_dw_ep0_xfer_complete(enum usb_dw_epdir epdir,
|
|
int status, int transferred)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(0, epdir);
|
|
|
|
switch((ep0.state << 1) | epdir)
|
|
{
|
|
case (EP0_DATA_IN << 1) | USB_DW_EPDIR_IN:
|
|
ep0.state = EP0_STATUS_OUT;
|
|
usb_dw_transfer(0, USB_DW_EPDIR_OUT, NULL, 0);
|
|
break;
|
|
|
|
case (EP0_DATA_OUT << 1) | USB_DW_EPDIR_OUT:
|
|
ep0.state = EP0_REQ;
|
|
usb_core_control_request(&ep0.active_req, dw_ep->req_addr);
|
|
break;
|
|
|
|
case (EP0_STATUS_IN << 1) | USB_DW_EPDIR_IN:
|
|
case (EP0_STATUS_OUT << 1) | USB_DW_EPDIR_OUT:
|
|
if(status != 0 || transferred != 0)
|
|
usb_core_control_complete(-2);
|
|
else
|
|
usb_core_control_complete(0);
|
|
|
|
ep0.state = EP0_SETUP;
|
|
break;
|
|
|
|
default:
|
|
panicf("%s: state=%s dir=%s", __func__,
|
|
dw_state_str[ep0.state], dw_dir_str[epdir]);
|
|
}
|
|
}
|
|
|
|
static void usb_dw_handle_xfer_complete(int epnum, enum usb_dw_epdir epdir)
|
|
{
|
|
struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
|
|
bool is_ep0out = (epnum == 0 && epdir == USB_DW_EPDIR_OUT);
|
|
|
|
if (!dw_ep->busy)
|
|
{
|
|
if(is_ep0out)
|
|
usb_dw_ep0_recv();
|
|
return;
|
|
}
|
|
|
|
uint32_t bytes_left = DWC_EPTSIZ(epnum, epdir) & 0x7ffff;
|
|
uint32_t transferred = (is_ep0out ? 64 : dw_ep->size) - bytes_left;
|
|
|
|
if(transferred > dw_ep->sizeleft)
|
|
{
|
|
/* Host sent more data than expected.
|
|
* Shouldn't happen for IN endpoints. */
|
|
dw_ep->status = -2;
|
|
goto complete;
|
|
}
|
|
|
|
if(is_ep0out)
|
|
{
|
|
#if defined(NO_UNCACHED_ADDR) && defined(POST_DMA_FLUSH)
|
|
DISCARD_DCACHE_RANGE(ep0_buffer, 64);
|
|
#endif
|
|
memcpy(dw_ep->addr, ep0_buffer, transferred);
|
|
usb_dw_ep0_recv();
|
|
}
|
|
|
|
dw_ep->sizeleft -= transferred;
|
|
|
|
/* Start a new transfer if there is still more to go */
|
|
if(bytes_left == 0 && dw_ep->sizeleft > 0)
|
|
{
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
dw_ep->addr += (dw_ep->size >> 2); /* offset in words */
|
|
#endif
|
|
usb_dw_epstart(epnum, epdir, dw_ep->addr, dw_ep->sizeleft);
|
|
return;
|
|
}
|
|
|
|
if(epdir == USB_DW_EPDIR_IN)
|
|
{
|
|
/* SNAK the disabled EP, otherwise IN tokens for this
|
|
EP could raise unwanted EPMIS interrupts. Useful for
|
|
usbserial when there is no data to send. */
|
|
DWC_DIEPCTL(epnum) |= SNAK;
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
/* See usb-s5l8701.c */
|
|
if (usb_dw_config.use_ptxfifo_as_plain_buffer)
|
|
{
|
|
int dtxfnum = GET_DTXFNUM(epnum);
|
|
if (dtxfnum)
|
|
usb_dw_flush_fifo(TXFFLSH, dtxfnum);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if !defined(USB_DW_ARCH_SLAVE) && defined(POST_DMA_FLUSH)
|
|
/* On EP0 OUT we do not DMA into the request buffer,
|
|
* so do not discard the cache in this case. */
|
|
if(!is_ep0out)
|
|
DISCARD_DCACHE_RANGE(dw_ep->req_addr, dw_ep->req_size);
|
|
#endif
|
|
}
|
|
|
|
dw_ep->status = 0;
|
|
|
|
complete:
|
|
dw_ep->busy = false;
|
|
semaphore_release(&dw_ep->complete);
|
|
|
|
int total_bytes = dw_ep->req_size - dw_ep->sizeleft;
|
|
if (epnum == 0)
|
|
{
|
|
usb_dw_ep0_xfer_complete(epdir, dw_ep->status, total_bytes);
|
|
}
|
|
else
|
|
{
|
|
usb_core_transfer_complete(epnum, (epdir == USB_DW_EPDIR_OUT) ?
|
|
USB_DIR_OUT : USB_DIR_IN, dw_ep->status, total_bytes);
|
|
}
|
|
}
|
|
|
|
static void usb_dw_handle_setup_received(void)
|
|
{
|
|
#if defined(NO_UNCACHED_ADDR) && defined(POST_DMA_FLUSH)
|
|
DISCARD_DCACHE_RANGE(ep0_buffer, 64);
|
|
#endif
|
|
struct usb_ctrlrequest req;
|
|
memcpy(&req, ep0_buffer, sizeof(struct usb_ctrlrequest));
|
|
|
|
usb_dw_ep0_recv();
|
|
|
|
usb_dw_control_received(&req);
|
|
}
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
static int usb_dw_get_epmis(void)
|
|
{
|
|
unsigned epmis;
|
|
uint32_t gnptxsts = DWC_GNPTXSTS;
|
|
|
|
if (((gnptxsts >> 16) & 0xff) >= hw_nptxqdepth)
|
|
return -1; /* empty queue */
|
|
|
|
/* Get the EP on the top of the queue, 0 < idx < number of available
|
|
IN endpoints */
|
|
uint32_t idx = (gnptxsts >> 27) & 0xf;
|
|
for (epmis = 0; epmis < USB_NUM_ENDPOINTS; epmis++)
|
|
if ((usb_endpoints & (1 << epmis)) && !idx--)
|
|
break;
|
|
|
|
/* The maximum EP mismatch counter is configured, so we verify all NPTX
|
|
queue entries, 4 bits per entry, first entry at DTKQNR1[11:8] */
|
|
uint32_t volatile *dtknqr = &DWC_DTKNQR1;
|
|
for (int i = 2; i < hw_nptxqdepth + 2; i++)
|
|
if (((*(dtknqr+(i>>3)) >> ((i & 0x7)*4)) & 0xf) == epmis)
|
|
return -1;
|
|
|
|
return epmis;
|
|
}
|
|
|
|
static void usb_dw_handle_token_mismatch(void)
|
|
{
|
|
usb_dw_ginak_effective(true);
|
|
int epmis = usb_dw_get_epmis();
|
|
if (epmis >= 0)
|
|
{
|
|
/* The EP is disabled, unqueued, and reconfigured to re-reenable it
|
|
later when a token is received, (or it will be cancelled by
|
|
timeout if it was a blocking request). */
|
|
usb_dw_nptx_unqueue(epmis);
|
|
|
|
epmis_msk |= (1 << epmis);
|
|
if (epmis_msk)
|
|
DWC_DIEPMSK |= ITTXFE;
|
|
|
|
/* Be sure the status is clear */
|
|
DWC_DIEPINT(epmis) = ITTXFE;
|
|
|
|
/* Must disable NAK to allow to get ITTXFE interrupts for this EP */
|
|
DWC_DIEPCTL(epmis) |= CNAK;
|
|
}
|
|
usb_dw_ginak_effective(false);
|
|
}
|
|
#endif /* USB_DW_SHARED_FIFO */
|
|
|
|
static void usb_dw_irq(void)
|
|
{
|
|
int ep;
|
|
uint32_t daint;
|
|
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
/* Handle one packet at a time, the IRQ will re-trigger if there's
|
|
something left. */
|
|
if (DWC_GINTSTS & RXFLVL)
|
|
{
|
|
usb_dw_handle_rxfifo();
|
|
}
|
|
#endif
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if (DWC_GINTSTS & EPMIS)
|
|
{
|
|
usb_dw_handle_token_mismatch();
|
|
DWC_GINTSTS = EPMIS;
|
|
}
|
|
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
uint32_t gintsts = DWC_GINTSTS & DWC_GINTMSK;
|
|
if (gintsts & PTXFE)
|
|
{
|
|
/* First disable the IRQ, it will be re-enabled later if there
|
|
is anything left to be done. */
|
|
DWC_GINTMSK &= ~PTXFE;
|
|
/* Check all periodic endpoints for anything to be transmitted */
|
|
for (ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
|
|
if (usb_endpoints & ep_periodic_msk & (1 << ep))
|
|
usb_dw_try_push(ep);
|
|
}
|
|
|
|
if (gintsts & NPTXFE)
|
|
{
|
|
/* First disable the IRQ, it will be re-enabled later if there
|
|
is anything left to be done. */
|
|
DWC_GINTMSK &= ~NPTXFE;
|
|
/* Check all non-periodic endpoints for anything to be transmitted */
|
|
for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
if (usb_endpoints & ~ep_periodic_msk & (1 << ep))
|
|
usb_dw_try_push(ep);
|
|
}
|
|
#endif /* USB_DW_ARCH_SLAVE */
|
|
#endif /* USB_DW_SHARED_FIFO */
|
|
|
|
daint = DWC_DAINT;
|
|
|
|
/* IN */
|
|
for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
{
|
|
if (daint & (1 << ep))
|
|
{
|
|
uint32_t epints = DWC_DIEPINT(ep);
|
|
|
|
if (epints & TOC)
|
|
{
|
|
usb_dw_abort_endpoint(ep, USB_DW_EPDIR_IN);
|
|
}
|
|
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if (epints & ITTXFE)
|
|
{
|
|
if (epmis_msk & (1 << ep))
|
|
{
|
|
DWC_DIEPCTL(ep) |= EPENA;
|
|
epmis_msk &= ~(1 << ep);
|
|
if (!epmis_msk)
|
|
DWC_DIEPMSK &= ~ITTXFE;
|
|
}
|
|
}
|
|
|
|
#elif defined(USB_DW_ARCH_SLAVE)
|
|
if (epints & TXFE)
|
|
{
|
|
usb_dw_handle_dtxfifo(ep);
|
|
}
|
|
#endif
|
|
|
|
/* Clear XFRC here, if this is a 'multi-transfer' request then
|
|
a new transfer is going to be launched, this ensures it will
|
|
not miss a single interrupt. */
|
|
DWC_DIEPINT(ep) = epints;
|
|
|
|
if (epints & XFRC)
|
|
{
|
|
usb_dw_handle_xfer_complete(ep, USB_DW_EPDIR_IN);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* OUT */
|
|
for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
{
|
|
if (daint & (1 << (ep + 16)))
|
|
{
|
|
uint32_t epints = DWC_DOEPINT(ep);
|
|
DWC_DOEPINT(ep) = epints;
|
|
|
|
if (!ep)
|
|
{
|
|
if (epints & STUP)
|
|
{
|
|
usb_dw_handle_setup_received();
|
|
}
|
|
|
|
if (epints & XFRC)
|
|
{
|
|
if(epints & STATUSRECVD)
|
|
{
|
|
/* At the end of a control write's data phase, the
|
|
* controller writes a spurious OUTDONE token to the
|
|
* FIFO and raises StatusRecvd | XferCompl.
|
|
*
|
|
* We do not need or want this -- we've already handled
|
|
* the data phase by this point -- but EP0 is stoppped
|
|
* as a side effect of XferCompl, so we need to restart
|
|
* it to keep receiving packets. */
|
|
usb_dw_ep0_recv();
|
|
}
|
|
else if(!(epints & SETUPRECVD))
|
|
{
|
|
/* Only call this for normal data packets. Setup
|
|
* packets use the STUP interrupt handler instead. */
|
|
usb_dw_handle_xfer_complete(0, USB_DW_EPDIR_OUT);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (epints & XFRC)
|
|
{
|
|
usb_dw_handle_xfer_complete(ep, USB_DW_EPDIR_OUT);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (DWC_GINTSTS & USBRST)
|
|
{
|
|
DWC_GINTSTS = USBRST;
|
|
usb_dw_set_address(0);
|
|
usb_dw_reset_endpoints();
|
|
usb_core_bus_reset();
|
|
}
|
|
|
|
if (DWC_GINTSTS & ENUMDNE)
|
|
{
|
|
DWC_GINTSTS = ENUMDNE;
|
|
ep0.state = EP0_SETUP;
|
|
usb_dw_ep0_recv();
|
|
}
|
|
}
|
|
|
|
static void usb_dw_check_hw(void)
|
|
{
|
|
uint32_t ghwcfg2 = DWC_GHWCFG2;
|
|
uint32_t ghwcfg3 = DWC_GHWCFG3;
|
|
uint32_t ghwcfg4 = DWC_GHWCFG4;
|
|
const struct usb_dw_config *c = &usb_dw_config;
|
|
int hw_numeps;
|
|
int hw_maxtxfifos; /* periodic or dedicated */
|
|
char *err;
|
|
|
|
hw_numeps = ((ghwcfg2 >> 10) & 0xf) + 1;
|
|
|
|
if (hw_numeps < USB_NUM_ENDPOINTS)
|
|
{
|
|
err = "USB_NUM_ENDPOINTS too big";
|
|
goto panic;
|
|
}
|
|
/* HWCFG registers are not checked to detect the PHY, if an option
|
|
is not supported then the related bits should be Read-Only. */
|
|
DWC_GUSBCFG = c->phytype;
|
|
if (DWC_GUSBCFG != c->phytype)
|
|
{
|
|
err = "PHY type not supported";
|
|
goto panic;
|
|
}
|
|
#ifndef USB_DW_ARCH_SLAVE
|
|
if (((ghwcfg2 >> 3) & 3) != 2)
|
|
{
|
|
err = "internal DMA not supported";
|
|
goto panic;
|
|
}
|
|
#endif
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if ((ghwcfg4 >> 25) & 1)
|
|
{
|
|
err = "shared TxFIFO not supported";
|
|
goto panic;
|
|
}
|
|
hw_maxtxfifos = ghwcfg4 & 0xf;
|
|
hw_nptxqdepth = (1 << (((ghwcfg2 >> 22) & 3) + 1));
|
|
#else
|
|
if (!((ghwcfg4 >> 25) & 1))
|
|
{
|
|
err = "dedicated TxFIFO not supported";
|
|
goto panic;
|
|
}
|
|
hw_maxtxfifos = (ghwcfg4 >> 26) & 0xf;
|
|
#endif
|
|
hw_maxbytes = (1 << (((ghwcfg3 >> 0) & 0xf) + 11)) - 1;
|
|
hw_maxpackets = (1 << (((ghwcfg3 >> 4) & 0x7) + 4)) - 1;
|
|
uint16_t hw_fifomem = ghwcfg3 >> 16;
|
|
|
|
/* Configure FIFOs, sizes are 32-bit words, we will need at least
|
|
one periodic or dedicated Tx FIFO (really the periodic Tx FIFO
|
|
is not needed if !USB_ENABLE_HID). */
|
|
if (c->rx_fifosz + c->nptx_fifosz + c->ptx_fifosz > hw_fifomem)
|
|
{
|
|
err = "insufficient FIFO memory";
|
|
goto panic;
|
|
}
|
|
n_ptxfifos = (hw_fifomem - c->rx_fifosz - c->nptx_fifosz) / c->ptx_fifosz;
|
|
if (n_ptxfifos > hw_maxtxfifos) n_ptxfifos = hw_maxtxfifos;
|
|
|
|
logf("%s():", __func__);
|
|
logf(" HW version: %4lx, num EPs: %d", DWC_GSNPSID & 0xffff, hw_numeps);
|
|
logf(" FIFO mem=%d rx=%d nptx=%d ptx=%dx%d", hw_fifomem,
|
|
c->rx_fifosz, c->nptx_fifosz, n_ptxfifos, c->ptx_fifosz);
|
|
|
|
return;
|
|
|
|
panic:
|
|
panicf("%s: %s", __func__, err);
|
|
}
|
|
|
|
static void usb_dw_init(void)
|
|
{
|
|
static bool initialized = false;
|
|
const struct usb_dw_config *c = &usb_dw_config;
|
|
|
|
if (!initialized)
|
|
{
|
|
#if !defined(USB_DW_ARCH_SLAVE) && !defined(NO_UNCACHED_ADDR)
|
|
ep0_buffer = USB_DW_UNCACHEDADDR(&_ep0_buffer[0]);
|
|
#else
|
|
/* DMA is not used so we can operate on cached addresses */
|
|
ep0_buffer = &_ep0_buffer[0];
|
|
#endif
|
|
|
|
for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
|
|
for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
|
|
semaphore_init(&usb_dw_get_ep(ep, dir)->complete, 1, 0);
|
|
|
|
initialized = true;
|
|
}
|
|
|
|
/* Disable IRQ during setup */
|
|
usb_dw_target_disable_irq();
|
|
|
|
/* Enable OTG clocks */
|
|
usb_dw_target_enable_clocks();
|
|
|
|
/* Enable PHY clocks */
|
|
DWC_PCGCCTL = 0;
|
|
|
|
usb_dw_check_hw();
|
|
|
|
/* Configure PHY type (must be done before reset) */
|
|
#ifndef USB_DW_TURNAROUND
|
|
/*
|
|
* Turnaround time (in PHY clocks) = 4*AHB clocks + 1*PHY clock,
|
|
* worst cases are:
|
|
* 16-bit UTMI+: PHY=30MHz, AHB=30Mhz -> 5
|
|
* 8-bit UTMI+: PHY=60MHz, AHB=30MHz -> 9
|
|
*/
|
|
int USB_DW_TURNAROUND = (c->phytype == DWC_PHYTYPE_UTMI_16) ? 5 : 9;
|
|
#endif
|
|
uint32_t gusbcfg = c->phytype|TRDT(USB_DW_TURNAROUND)|USB_DW_TOUTCAL;
|
|
DWC_GUSBCFG = gusbcfg;
|
|
|
|
/* Reset the whole USB core */
|
|
udelay(100);
|
|
usb_dw_wait_for_ahb_idle();
|
|
DWC_GRSTCTL = CSRST;
|
|
while (DWC_GRSTCTL & CSRST);
|
|
usb_dw_wait_for_ahb_idle();
|
|
|
|
/* Configure FIFOs */
|
|
DWC_GRXFSIZ = c->rx_fifosz;
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
DWC_GNPTXFSIZ = (c->nptx_fifosz << 16) | c->rx_fifosz;
|
|
#else
|
|
DWC_TX0FSIZ = (c->nptx_fifosz << 16) | c->rx_fifosz;
|
|
#endif
|
|
for (int i = 0; i < n_ptxfifos; i++)
|
|
DWC_DIEPTXF(i) = (c->ptx_fifosz << 16) |
|
|
(c->nptx_fifosz + c->rx_fifosz + c->ptx_fifosz*i);
|
|
/*
|
|
* According to p428 of the design guide, we need to ensure that
|
|
* fifos are flushed before continuing.
|
|
*/
|
|
usb_dw_flush_fifo(TXFFLSH|RXFFLSH, 0x10);
|
|
|
|
/* Configure the core */
|
|
DWC_GUSBCFG = gusbcfg;
|
|
|
|
uint32_t gahbcfg = GINT;
|
|
#ifdef USB_DW_ARCH_SLAVE
|
|
#ifdef USB_DW_SHARED_FIFO
|
|
if (c->use_ptxfifo_as_plain_buffer)
|
|
gahbcfg |= PTXFELVL;
|
|
#endif
|
|
if (c->disable_double_buffering)
|
|
gahbcfg |= TXFELVL;
|
|
#else
|
|
gahbcfg |= HBSTLEN(c->ahb_burst_len)|DMAEN;
|
|
#endif
|
|
DWC_GAHBCFG = gahbcfg;
|
|
|
|
DWC_DCFG = NZLSOHSK;
|
|
#ifdef USB_DW_SHARED_FIFO
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/* Set EP mismatch counter to the maximum */
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DWC_DCFG |= EPMISCNT(0x1f);
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#endif
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#if !defined(USB_DW_ARCH_SLAVE) && !defined(USB_DW_SHARED_FIFO)
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if (c->ahb_threshold)
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DWC_DTHRCTL = ARPEN|RXTHRLEN(c->ahb_threshold)|RXTHREN;
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#endif
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/* Set up interrupts */
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DWC_DOEPMSK = STUP|XFRC;
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DWC_DIEPMSK = TOC|XFRC;
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/* Unmask all available endpoints */
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DWC_DAINTMSK = 0xffffffff;
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usb_endpoints = DWC_DAINTMSK;
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uint32_t gintmsk = USBRST|ENUMDNE|IEPINT|OEPINT;
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#ifdef USB_DW_ARCH_SLAVE
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gintmsk |= RXFLVL;
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#endif
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#ifdef USB_DW_SHARED_FIFO
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gintmsk |= EPMIS;
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#endif
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DWC_GINTMSK = gintmsk;
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usb_dw_reset_endpoints();
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/* Soft disconnect */
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DWC_DCTL = SDIS;
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usb_dw_target_clear_irq();
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usb_dw_target_enable_irq();
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/* Soft reconnect */
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udelay(3000);
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DWC_DCTL &= ~SDIS;
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}
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static void usb_dw_exit(void)
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{
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/* Soft disconnect */
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DWC_DCTL = SDIS;
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udelay(10);
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DWC_PCGCCTL = 1; /* Stop Phy clock */
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/* Disable IRQs */
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usb_dw_target_disable_irq();
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/* Disable clocks */
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usb_dw_target_disable_clocks();
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}
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/*
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* API functions
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*/
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/* Cancel transfers on configured EPs */
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void usb_drv_cancel_all_transfers()
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{
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usb_dw_target_disable_irq();
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for (int ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
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for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
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if (usb_endpoints & (1 << (ep + USB_DW_DIR_OFF(dir))))
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if (usb_dw_get_ep(ep, dir)->active)
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{
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//usb_dw_flush_endpoint(ep, dir);
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usb_dw_abort_endpoint(ep, dir);
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DWC_EPCTL(ep, dir) |= SD0PID;
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}
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usb_dw_target_enable_irq();
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}
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bool usb_drv_stalled(int endpoint, bool in)
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{
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return usb_dw_get_stall(EP_NUM(endpoint),
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in ? USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT);
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}
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void usb_drv_stall(int endpoint, bool stall, bool in)
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{
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usb_dw_target_disable_irq();
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usb_dw_set_stall(EP_NUM(endpoint),
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in ? USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT, stall);
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usb_dw_target_enable_irq();
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}
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void usb_drv_set_address(int address)
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{
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#if 1
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/* Ignored intentionally, because the controller requires us to set the
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new address before sending the response for some reason. So we'll
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already set it when the control request arrives, before passing that
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into the USB core, which will then call this dummy function. */
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(void)address;
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#else
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usb_dw_target_disable_irq();
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usb_dw_set_address(address);
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usb_dw_target_enable_irq();
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#endif
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}
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int usb_drv_port_speed(void)
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{
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return ((DWC_DSTS & 0x6) == 0);
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}
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void usb_drv_set_test_mode(int mode)
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{
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(void)mode;
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/* Ignore this for now */
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}
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void usb_attach(void)
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{
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}
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void usb_drv_init(void)
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{
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usb_dw_init();
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}
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void usb_drv_exit(void)
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{
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usb_dw_exit();
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}
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void INT_USB_FUNC(void)
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{
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usb_dw_irq();
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}
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int usb_drv_request_endpoint(int type, int dir)
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{
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int request_ep = -1;
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enum usb_dw_epdir epdir = (EP_DIR(dir) == DIR_IN) ?
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USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT;
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usb_dw_target_disable_irq();
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for (int ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
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{
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if (usb_endpoints & (1 << (ep + USB_DW_DIR_OFF(epdir))))
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{
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, epdir);
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if (!dw_ep->active)
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{
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if (usb_dw_configure_ep(ep, epdir, type,
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usb_drv_port_speed() ? 512 : 64) >= 0)
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{
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dw_ep->active = true;
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request_ep = ep | dir;
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}
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break;
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}
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}
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}
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usb_dw_target_enable_irq();
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return request_ep;
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}
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void usb_drv_release_endpoint(int endpoint)
|
|
{
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int epnum = EP_NUM(endpoint);
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if (!epnum) return;
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enum usb_dw_epdir epdir = (EP_DIR(endpoint) == DIR_IN) ?
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USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT;
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
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usb_dw_target_disable_irq();
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if (dw_ep->active)
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{
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usb_dw_unconfigure_ep(epnum, epdir);
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dw_ep->active = false;
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}
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usb_dw_target_enable_irq();
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}
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int usb_drv_recv_nonblocking(int endpoint, void* ptr, int length)
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{
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usb_dw_target_disable_irq();
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usb_dw_transfer(EP_NUM(endpoint), USB_DW_EPDIR_OUT, ptr, length);
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usb_dw_target_enable_irq();
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return 0;
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}
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int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
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{
|
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usb_dw_target_disable_irq();
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usb_dw_transfer(EP_NUM(endpoint), USB_DW_EPDIR_IN, ptr, length);
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usb_dw_target_enable_irq();
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return 0;
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}
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int usb_drv_send(int endpoint, void *ptr, int length)
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{
|
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int epnum = EP_NUM(endpoint);
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struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
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semaphore_wait(&dw_ep->complete, 0);
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usb_drv_send_nonblocking(endpoint, ptr, length);
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if (semaphore_wait(&dw_ep->complete, HZ) == OBJ_WAIT_TIMEDOUT)
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{
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usb_dw_target_disable_irq();
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usb_dw_abort_endpoint(epnum, USB_DW_EPDIR_IN);
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usb_dw_target_enable_irq();
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}
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return dw_ep->status;
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}
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|
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void usb_drv_control_response(enum usb_control_response resp,
|
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void* data, int length)
|
|
{
|
|
usb_dw_target_disable_irq();
|
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usb_dw_control_response(resp, data, length);
|
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usb_dw_target_enable_irq();
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}
|