eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
169 lines
6.5 KiB
C
169 lines
6.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __DMA_IMX233_H__
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#define __DMA_IMX233_H__
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#include "cpu.h"
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#include "system.h"
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#include "system-target.h"
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/************
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* CHANNELS *
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************/
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#define APBH_DMA_CHANNEL(i) i
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#define APBX_DMA_CHANNEL(i) ((i) | 0x10)
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#define APB_IS_APBX_CHANNEL(x) ((x) & 0x10)
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#define APB_GET_DMA_CHANNEL(x) ((x) & 0xf)
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#if IMX233_SUBTARGET >= 3700
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// NOTE: although undocumented, the iMX233 channel 0 is actually the LCDIF one
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#define APB_LCDIF APBH_DMA_CHANNEL(0)
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#else
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#define APB_LCDIF APBX_DMA_CHANNEL(4)
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#endif
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#define APB_SSP(ssp) APBH_DMA_CHANNEL(ssp)
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#define APB_GPMI(dev) APBH_DMA_CHANNEL(4 + (dev))
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#define APB_AUDIO_ADC APBX_DMA_CHANNEL(0)
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#define APB_AUDIO_DAC APBX_DMA_CHANNEL(1)
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#define APB_I2C APBX_DMA_CHANNEL(3)
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// NOTE: although undocumented, the IMX233 channel 5 is actually the DRI one
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#define APB_DRI APBX_DMA_CHANNEL(5)
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/**********
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* COMMON *
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**********/
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/* DMA structures should be cache aligned and be padded so that their size
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* is a multiple of a cache line size. Otherwise some nasty side effects
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* could occur with adjacents data fields.
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* The same apply to DMA buffers for the same reasons */
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struct apb_dma_command_t
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{
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struct apb_dma_command_t *next;
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uint32_t cmd;
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void *buffer;
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/* PIO words follow */
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} __attribute__((packed));
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#define DMA_INFO_CURCMDADDR (1 << 0)
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#define DMA_INFO_NXTCMDADDR (1 << 1)
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#define DMA_INFO_CMD (1 << 2)
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#define DMA_INFO_BAR (1 << 3)
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#define DMA_INFO_APB_BYTES (1 << 4)
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#define DMA_INFO_AHB_BYTES (1 << 5)
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#define DMA_INFO_FROZEN (1 << 6)
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#define DMA_INFO_GATED (1 << 7)
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#define DMA_INFO_INTERRUPT (1 << 8)
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#define DMA_INFO_ALL 0x1ff
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struct imx233_dma_info_t
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{
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unsigned long cur_cmd_addr;
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unsigned long nxt_cmd_addr;
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unsigned long cmd;
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unsigned long bar;
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unsigned apb_bytes;
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unsigned ahb_bytes;
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bool frozen;
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bool gated;
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bool int_enabled;
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bool int_cmdcomplt;
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bool int_error;
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int nr_unaligned;
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};
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#define BM_APB_CHx_CMD_COMMAND 0x3
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#define BP_APB_CHx_CMD_COMMAND 0
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#define BF_APB_CHx_CMD_COMMAND(v) ((v) & 0x3)
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#define BF_APB_CHx_CMD_COMMAND_V(v) BF_APB_CHx_CMD_COMMAND(BV_APB_CHx_CMD_COMMAND__##v)
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#define BV_APB_CHx_CMD_COMMAND__NO_XFER 0
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#define BV_APB_CHx_CMD_COMMAND__WRITE 1
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#define BV_APB_CHx_CMD_COMMAND__READ 2
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#define BV_APB_CHx_CMD_COMMAND__SENSE 3
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#define BM_APB_CHx_CMD_CHAIN (1 << 2)
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#define BP_APB_CHx_CMD_CHAIN 2
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#define BF_APB_CHx_CMD_CHAIN(v) (((v) & 1) << 2)
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#define BM_APB_CHx_CMD_IRQONCMPLT (1 << 3)
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#define BP_APB_CHx_CMD_IRQONCMPLT 3
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#define BF_APB_CHx_CMD_IRQONCMPLT(v) (((v) & 1) << 3)
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/* those two are only available on APHB */
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#define BM_APBH_CHx_CMD_NANDLOCK (1 << 4)
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#define BP_APBH_CHx_CMD_NANDLOCK 4
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#define BF_APBH_CHx_CMD_NANDLOCK(v) (((v) & 1) << 4)
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#define BM_APBH_CHx_CMD_NANDWAIT4READY (1 << 5)
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#define BP_APBH_CHx_CMD_NANDWAIT4READY 5
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#define BF_APBH_CHx_CMD_NANDWAIT4READY(v) (((v) & 1) << 5)
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#define BM_APB_CHx_CMD_SEMAPHORE (1 << 6)
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#define BP_APB_CHx_CMD_SEMAPHORE 6
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#define BF_APB_CHx_CMD_SEMAPHORE(v) (((v) & 1) << 6)
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#define BM_APB_CHx_CMD_WAIT4ENDCMD (1 << 7)
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#define BP_APB_CHx_CMD_WAIT4ENDCMD 7
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#define BF_APB_CHx_CMD_WAIT4ENDCMD(v) (((v) & 1) << 7)
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/** WARNING: An errata advise not to use it */
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#define BM_APB_CHx_CMD_HALTONTERMINATE (1 << 8)
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#define BP_APB_CHx_CMD_HALTONTERMINATE 8
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#define BF_APB_CHx_CMD_HALTONTERMINATE(v) (((v) & 1) << 8)
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#define BM_APB_CHx_CMD_CMDWORDS 0xf000
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#define BP_APB_CHx_CMD_CMDWORDS 12
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#define BF_APB_CHx_CMD_CMDWORDS(v) (((v) & 0xf) << 12)
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#define BM_APB_CHx_CMD_XFER_COUNT 0xffff0000
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#define BP_APB_CHx_CMD_XFER_COUNT 16
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#define BF_APB_CHx_CMD_XFER_COUNT(v) (((v) & 0xffff) << 16)
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/* For software use */
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#define BP_APB_CHx_CMD_UNUSED 8
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#define BM_APB_CHx_CMD_UNUSED (0xf << 8)
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#define BF_APB_CHx_CMD_UNUSED(v) (((v) & 0xf) << 8)
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#define BF_APB_CHx_CMD_UNUSED_V(n) BF_APB_CHx_CMD_UNUSED(BV_APB_CHx_CMD_UNUSED__##n)
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#define BFM_APB_CHx_CMD_UNUSED(v) BM_APB_CHx_CMD_UNUSED
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#define BV_APB_CHx_CMD_UNUSED__MAGIC 0xa
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#define BFM_APB_CHx_CMD_UNUSED_V(v) BM_APB_CHx_CMD_UNUSED
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/* A single descriptor cannot transfer more than 2^16 bytes but because of the
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* weird 0=64KiB, it's safer to restrict to 2^15 */
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#define IMX233_MAX_SINGLE_DMA_XFER_SIZE (1 << 16)
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void imx233_dma_init(void);
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void imx233_dma_reset_channel(unsigned chan);
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/* only apbh channel have clkgate control */
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void imx233_dma_clkgate_channel(unsigned chan, bool enable_clock);
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void imx233_dma_freeze_channel(unsigned chan, bool freeze);
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void imx233_dma_enable_channel_interrupt(unsigned chan, bool enable);
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/* clear both channel complete and error bits */
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void imx233_dma_clear_channel_interrupt(unsigned chan);
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bool imx233_dma_is_channel_error_irq(unsigned chan);
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/* assume no command is in progress */
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void imx233_dma_prepare_command(unsigned chan, struct apb_dma_command_t *cmd);
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void imx233_dma_set_next_command(unsigned chan, struct apb_dma_command_t *cmd);
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void imx233_dma_inc_sema(unsigned chan, unsigned amount);
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/* wrapper around prepare_command, set_next_command, inc_sema(1) */
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void imx233_dma_start_command(unsigned chan, struct apb_dma_command_t *cmd);
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/* return value of the semaphore */
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int imx233_dma_wait_completion(unsigned chan, unsigned tmo);
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/* get some info
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* WARNING: if channel is not freezed, data might not be coherent ! */
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struct imx233_dma_info_t imx233_dma_get_info(unsigned chan, unsigned flags);
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#endif // __DMA_IMX233_H__
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