2acc0ac542
later. We still need to hunt down snippets used that are not. 1324 modified files... http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
345 lines
9.5 KiB
C
345 lines
9.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (c) 2007 Will Robertson
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "spi-imx31.h"
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#include "avic-imx31.h"
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#include "clkctl-imx31.h"
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#include "debug.h"
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#include "kernel.h"
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/* Forward interrupt handler declarations */
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#if (SPI_MODULE_MASK & USE_CSPI1_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI1_HANDLER(void);
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI2_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI2_HANDLER(void);
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI3_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI3_HANDLER(void);
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#endif
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/* State data associatated with each CSPI module */
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static struct spi_module_descriptor
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{
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struct cspi_map * const base;
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int enab;
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struct spi_node *last;
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enum IMX31_CG_LIST cg;
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enum IMX31_INT_LIST ints;
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int byte_size;
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void (*handler)(void);
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struct mutex m;
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struct wakeup w;
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struct spi_transfer *trans;
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int rxcount;
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} spi_descs[SPI_NUM_CSPI] =
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/* Init non-zero members */
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{
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#if (SPI_MODULE_MASK & USE_CSPI1_MODULE)
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{
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.base = (struct cspi_map *)CSPI1_BASE_ADDR,
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.cg = CG_CSPI1,
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.ints = CSPI1,
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.handler = CSPI1_HANDLER,
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},
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI2_MODULE)
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{
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.base = (struct cspi_map *)CSPI2_BASE_ADDR,
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.cg = CG_CSPI2,
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.ints = CSPI2,
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.handler = CSPI2_HANDLER,
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},
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI3_MODULE)
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{
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.base = (struct cspi_map *)CSPI3_BASE_ADDR,
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.cg = CG_CSPI3,
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.ints = CSPI3,
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.handler = CSPI3_HANDLER,
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},
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#endif
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};
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/* Common code for interrupt handlers */
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static void spi_interrupt(enum spi_module_number spi)
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{
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struct spi_module_descriptor *desc = &spi_descs[spi];
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struct cspi_map * const base = desc->base;
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struct spi_transfer *trans = desc->trans;
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int inc = desc->byte_size + 1;
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if (desc->rxcount > 0)
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{
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/* Data received - empty out RXFIFO */
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while ((base->statreg & CSPI_STATREG_RR) != 0)
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{
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uint32_t word = base->rxdata;
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switch (desc->byte_size & 3)
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{
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case 3:
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*(unsigned char *)(trans->rxbuf + 3) = word >> 24;
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case 2:
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*(unsigned char *)(trans->rxbuf + 2) = word >> 16;
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case 1:
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*(unsigned char *)(trans->rxbuf + 1) = word >> 8;
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case 0:
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*(unsigned char *)(trans->rxbuf + 0) = word;
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}
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trans->rxbuf += inc;
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if (--desc->rxcount < 4)
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{
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unsigned long intreg = base->intreg;
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if (desc->rxcount <= 0)
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{
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/* No more to receive - stop RX interrupts */
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intreg &= ~(CSPI_INTREG_RHEN | CSPI_INTREG_RREN);
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base->intreg = intreg;
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break;
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}
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else if (!(intreg & CSPI_INTREG_RREN))
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{
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/* < 4 words expected - switch to RX ready */
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intreg &= ~CSPI_INTREG_RHEN;
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base->intreg = intreg | CSPI_INTREG_RREN;
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}
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}
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}
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}
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if (trans->count > 0)
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{
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/* Data to transmit - fill TXFIFO or write until exhausted */
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while ((base->statreg & CSPI_STATREG_TF) == 0)
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{
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uint32_t word = 0;
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switch (desc->byte_size & 3)
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{
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case 3:
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word = *(unsigned char *)(trans->txbuf + 3) << 24;
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case 2:
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word |= *(unsigned char *)(trans->txbuf + 2) << 16;
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case 1:
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word |= *(unsigned char *)(trans->txbuf + 1) << 8;
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case 0:
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word |= *(unsigned char *)(trans->txbuf + 0);
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}
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trans->txbuf += inc;
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base->txdata = word;
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if (--trans->count <= 0)
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{
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/* Out of data - stop TX interrupts */
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base->intreg &= ~CSPI_INTREG_THEN;
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break;
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}
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}
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}
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/* If all interrupts have been remasked - we're done */
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if (base->intreg == 0)
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{
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base->statreg = CSPI_STATREG_TC | CSPI_STATREG_BO;
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wakeup_signal(&desc->w);
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}
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}
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/* Interrupt handlers for each CSPI module */
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#if (SPI_MODULE_MASK & USE_CSPI1_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI1_HANDLER(void)
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{
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spi_interrupt(CSPI1_NUM);
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}
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI2_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI2_HANDLER(void)
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{
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spi_interrupt(CSPI2_NUM);
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}
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#endif
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#if (SPI_MODULE_MASK & USE_CSPI3_MODULE)
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static __attribute__((interrupt("IRQ"))) void CSPI3_HANDLER(void)
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{
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spi_interrupt(CSPI3_NUM);
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}
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#endif
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/* Write the context for the node and remember it to avoid unneeded reconfigure */
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static bool spi_set_context(struct spi_node *node,
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struct spi_module_descriptor *desc)
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{
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struct cspi_map * const base = desc->base;
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if ((base->conreg & CSPI_CONREG_EN) == 0)
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return false;
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if (node != desc->last)
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{
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/* Switch the module's node */
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desc->last = node;
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desc->byte_size = (((node->conreg >> 8) & 0x1f) + 1 + 7) / 8 - 1;
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/* Keep reserved and start bits cleared. Keep enabled bit. */
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base->conreg =
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(node->conreg & ~(0xfcc8e000 | CSPI_CONREG_XCH | CSPI_CONREG_SMC))
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| CSPI_CONREG_EN;
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/* Set the wait-states */
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base->periodreg = node->periodreg & 0xffff;
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/* Clear out any spuriously-pending interrupts */
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base->statreg = CSPI_STATREG_TC | CSPI_STATREG_BO;
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}
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return true;
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}
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/* Initialize each of the used SPI descriptors */
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void spi_init(void)
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{
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int i;
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for (i = 0; i < SPI_NUM_CSPI; i++)
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{
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struct spi_module_descriptor * const desc = &spi_descs[i];
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mutex_init(&desc->m);
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wakeup_init(&desc->w);
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}
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}
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/* Get mutually-exclusive access to the node */
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void spi_lock(struct spi_node *node)
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{
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mutex_lock(&spi_descs[node->num].m);
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}
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/* Release mutual exclusion */
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void spi_unlock(struct spi_node *node)
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{
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mutex_unlock(&spi_descs[node->num].m);
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}
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/* Enable the specified module for the node */
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void spi_enable_module(struct spi_node *node)
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{
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struct spi_module_descriptor * const desc = &spi_descs[node->num];
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mutex_lock(&desc->m);
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if (++desc->enab == 1)
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{
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/* First enable for this module */
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struct cspi_map * const base = desc->base;
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/* Enable clock-gating register */
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imx31_clkctl_module_clock_gating(desc->cg, CGM_ON_ALL);
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/* Reset */
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base->conreg &= ~CSPI_CONREG_EN;
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base->conreg |= CSPI_CONREG_EN;
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base->intreg = 0;
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base->statreg = CSPI_STATREG_TC | CSPI_STATREG_BO;
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/* Enable interrupt at controller level */
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avic_enable_int(desc->ints, IRQ, 6, desc->handler);
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}
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mutex_unlock(&desc->m);
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}
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/* Disabled the specified module for the node */
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void spi_disable_module(struct spi_node *node)
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{
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struct spi_module_descriptor * const desc = &spi_descs[node->num];
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mutex_lock(&desc->m);
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if (desc->enab > 0 && --desc->enab == 0)
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{
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/* Last enable for this module */
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struct cspi_map * const base = desc->base;
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/* Disable interrupt at controller level */
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avic_disable_int(desc->ints);
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/* Disable interface */
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base->conreg &= ~CSPI_CONREG_EN;
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/* Disable interface clock */
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imx31_clkctl_module_clock_gating(desc->cg, CGM_OFF);
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}
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mutex_unlock(&desc->m);
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}
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/* Send and/or receive data on the specified node */
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int spi_transfer(struct spi_node *node, struct spi_transfer *trans)
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{
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struct spi_module_descriptor * const desc = &spi_descs[node->num];
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int retval;
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if (trans->count <= 0)
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return true;
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mutex_lock(&desc->m);
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retval = spi_set_context(node, desc);
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if (retval)
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{
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struct cspi_map * const base = desc->base;
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unsigned long intreg;
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desc->trans = trans;
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desc->rxcount = trans->count;
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/* Enable needed interrupts - FIFOs will start filling */
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intreg = CSPI_INTREG_THEN;
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intreg |= (trans->count < 4) ?
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CSPI_INTREG_RREN : /* Must grab data on every word */
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CSPI_INTREG_RHEN; /* Enough data to wait for half-full */
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base->intreg = intreg;
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/* Start transfer */
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base->conreg |= CSPI_CONREG_XCH;
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if (wakeup_wait(&desc->w, HZ) != OBJ_WAIT_SUCCEEDED)
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{
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base->intreg = 0;
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base->conreg &= ~CSPI_CONREG_XCH;
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retval = false;
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}
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}
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mutex_unlock(&desc->m);
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return retval;
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}
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