112 lines
4.8 KiB
C
112 lines
4.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* x1000 version: 1.0
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* x1000 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_DMA_H__
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#define __HEADERGEN_DMA_H__
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#include "macro.h"
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#define REG_DMA_CTRL jz_reg(DMA_CTRL)
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#define JA_DMA_CTRL (0xb3421000 + 0x0)
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#define JT_DMA_CTRL JIO_32_RW
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#define JN_DMA_CTRL DMA_CTRL
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#define JI_DMA_CTRL
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#define BP_DMA_CTRL_FMSC 31
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#define BM_DMA_CTRL_FMSC 0x80000000
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#define BF_DMA_CTRL_FMSC(v) (((v) & 0x1) << 31)
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#define BFM_DMA_CTRL_FMSC(v) BM_DMA_CTRL_FMSC
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#define BF_DMA_CTRL_FMSC_V(e) BF_DMA_CTRL_FMSC(BV_DMA_CTRL_FMSC__##e)
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#define BFM_DMA_CTRL_FMSC_V(v) BM_DMA_CTRL_FMSC
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#define BP_DMA_CTRL_FSSI 30
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#define BM_DMA_CTRL_FSSI 0x40000000
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#define BF_DMA_CTRL_FSSI(v) (((v) & 0x1) << 30)
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#define BFM_DMA_CTRL_FSSI(v) BM_DMA_CTRL_FSSI
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#define BF_DMA_CTRL_FSSI_V(e) BF_DMA_CTRL_FSSI(BV_DMA_CTRL_FSSI__##e)
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#define BFM_DMA_CTRL_FSSI_V(v) BM_DMA_CTRL_FSSI
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#define BP_DMA_CTRL_FTSSI 29
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#define BM_DMA_CTRL_FTSSI 0x20000000
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#define BF_DMA_CTRL_FTSSI(v) (((v) & 0x1) << 29)
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#define BFM_DMA_CTRL_FTSSI(v) BM_DMA_CTRL_FTSSI
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#define BF_DMA_CTRL_FTSSI_V(e) BF_DMA_CTRL_FTSSI(BV_DMA_CTRL_FTSSI__##e)
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#define BFM_DMA_CTRL_FTSSI_V(v) BM_DMA_CTRL_FTSSI
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#define BP_DMA_CTRL_FUART 28
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#define BM_DMA_CTRL_FUART 0x10000000
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#define BF_DMA_CTRL_FUART(v) (((v) & 0x1) << 28)
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#define BFM_DMA_CTRL_FUART(v) BM_DMA_CTRL_FUART
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#define BF_DMA_CTRL_FUART_V(e) BF_DMA_CTRL_FUART(BV_DMA_CTRL_FUART__##e)
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#define BFM_DMA_CTRL_FUART_V(v) BM_DMA_CTRL_FUART
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#define BP_DMA_CTRL_FAIC 27
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#define BM_DMA_CTRL_FAIC 0x8000000
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#define BF_DMA_CTRL_FAIC(v) (((v) & 0x1) << 27)
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#define BFM_DMA_CTRL_FAIC(v) BM_DMA_CTRL_FAIC
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#define BF_DMA_CTRL_FAIC_V(e) BF_DMA_CTRL_FAIC(BV_DMA_CTRL_FAIC__##e)
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#define BFM_DMA_CTRL_FAIC_V(v) BM_DMA_CTRL_FAIC
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#define BP_DMA_CTRL_HALT 3
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#define BM_DMA_CTRL_HALT 0x8
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#define BF_DMA_CTRL_HALT(v) (((v) & 0x1) << 3)
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#define BFM_DMA_CTRL_HALT(v) BM_DMA_CTRL_HALT
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#define BF_DMA_CTRL_HALT_V(e) BF_DMA_CTRL_HALT(BV_DMA_CTRL_HALT__##e)
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#define BFM_DMA_CTRL_HALT_V(v) BM_DMA_CTRL_HALT
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#define BP_DMA_CTRL_AR 2
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#define BM_DMA_CTRL_AR 0x4
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#define BF_DMA_CTRL_AR(v) (((v) & 0x1) << 2)
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#define BFM_DMA_CTRL_AR(v) BM_DMA_CTRL_AR
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#define BF_DMA_CTRL_AR_V(e) BF_DMA_CTRL_AR(BV_DMA_CTRL_AR__##e)
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#define BFM_DMA_CTRL_AR_V(v) BM_DMA_CTRL_AR
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#define BP_DMA_CTRL_ENABLE 0
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#define BM_DMA_CTRL_ENABLE 0x1
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#define BF_DMA_CTRL_ENABLE(v) (((v) & 0x1) << 0)
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#define BFM_DMA_CTRL_ENABLE(v) BM_DMA_CTRL_ENABLE
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#define BF_DMA_CTRL_ENABLE_V(e) BF_DMA_CTRL_ENABLE(BV_DMA_CTRL_ENABLE__##e)
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#define BFM_DMA_CTRL_ENABLE_V(v) BM_DMA_CTRL_ENABLE
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#define REG_DMA_IRQP jz_reg(DMA_IRQP)
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#define JA_DMA_IRQP (0xb3421000 + 0x4)
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#define JT_DMA_IRQP JIO_32_RW
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#define JN_DMA_IRQP DMA_IRQP
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#define JI_DMA_IRQP
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#define REG_DMA_DB jz_reg(DMA_DB)
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#define JA_DMA_DB (0xb3421000 + 0x8)
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#define JT_DMA_DB JIO_32_RW
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#define JN_DMA_DB DMA_DB
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#define JI_DMA_DB
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#define REG_DMA_DB_SET jz_reg(DMA_DB_SET)
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#define JA_DMA_DB_SET (JA_DMA_DB + 0x4)
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#define JT_DMA_DB_SET JIO_32_WO
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#define JN_DMA_DB_SET DMA_DB
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#define JI_DMA_DB_SET
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#define REG_DMA_DIP jz_reg(DMA_DIP)
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#define JA_DMA_DIP (0xb3421000 + 0x10)
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#define JT_DMA_DIP JIO_32_RW
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#define JN_DMA_DIP DMA_DIP
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#define JI_DMA_DIP
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#define REG_DMA_DIC jz_reg(DMA_DIC)
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#define JA_DMA_DIC (0xb3421000 + 0x14)
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#define JT_DMA_DIC JIO_32_RW
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#define JN_DMA_DIC DMA_DIC
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#define JI_DMA_DIC
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#endif /* __HEADERGEN_DMA_H__*/
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