7552542288
This test software setups timer T0 periodic interrupt. In ISR it changes backlight level. The interrupt handler does not support nesting and the whole ISR is run in interrupt context. Exceptions are not handled yet. Change-Id: Idc5d622991c7257b4577448d8be08ddd1c24c745
98 lines
2.3 KiB
ArmAsm
98 lines
2.3 KiB
ArmAsm
#include "mips.h"
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.extern main
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.global start
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.set mips32r2
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.set noreorder
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.set noat
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.section .init.text,"ax",%progbits
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start:
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di # disable interrupts
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bltzal zero, load_addr # ra = PC + 8, branch not taken
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nop
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load_addr:
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addiu v0, ra, -12 # calc real load address
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# account for branch delay slot
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# and very first 'di' instruction
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la t0, relocstart
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la t1, relocend
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beq t0, v0, entry_point # no relocation needed
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nop
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reloc_loop:
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lw t2, 0(v0) # src
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addiu v0, 4 # inc src addr
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sw t2, 0(t0) # dst
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bne t0, t1, reloc_loop
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addiu t0, 4 # inc dst addr
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entry_point_jump:
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la t0, entry_point
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jr t0
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nop
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entry_point:
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# setup caches
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# 4-way, 256 sets, 16 bytes cacheline I/D
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li t0, 3 # enable cache for kseg0 accesses
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mtc0 t0, C0_CONFIG
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la t0, 0x80000000 # an idx op should use an unmappable address
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ori t1, t0, 0x4000 # 16kB cache
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mtc0 zero, C0_TAGLO
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mtc0 zero, C0_TAGHI
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cache_init_loop:
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cache 8, 0(t0) # index store icache tag
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cache 9, 0(t0) # index store dcache tag
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bne t0, t1, cache_init_loop
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addiu t0, t0, 0x10
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intc_setup:
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li t0, 0xb0020000 # INTC base
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lw zero, 4(t0) # INTC_MSK mask all interrupt sources
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core_irq_setup:
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li t0, 0x00404000 # BEV=1 for C0_EBASE setup, IM6=1, IE=0
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mtc0 t0, C0_STATUS
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la t0, _irqbase # vectors base address must be 4k aligned
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mtc0 t0, C0_EBASE
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li t0, 0x00004000
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mtc0 t0, C0_STATUS # BEV=0, IM6=1, IE=0
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li t1, 0x08800000
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mtc0 t1, C0_CAUSE # DC=1, IV=1
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mtc0 zero,C0_INTCTL # VS = 0
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# clear bss
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la t0, bssbegin
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la t1, bssend
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clear_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, clear_bss_loop
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addiu t0, 4
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# setup stack
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la k0, irqstackend
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la sp, stackend
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la t0, stackbegin
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li t1, 0xdeadbeef
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stack_munge_loop:
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sw t1, 0(t0)
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bne t0, sp, stack_munge_loop
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addiu t0, 4
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# jump to C code with enabled interrupts
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j main
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ei
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.set at
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.set reorder
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