134 lines
6.3 KiB
C
134 lines
6.3 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3600:2.3.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__PWM__H__
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#define __HEADERGEN__STMP3600__PWM__H__
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#define REGS_PWM_BASE (0x80064000)
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#define REGS_PWM_VERSION "2.3.0"
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/**
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* Register: HW_PWM_CTRL
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* Address: 0
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* SCT: yes
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*/
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#define HW_PWM_CTRL (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x0))
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#define HW_PWM_CTRL_SET (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x4))
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#define HW_PWM_CTRL_CLR (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0x8))
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#define HW_PWM_CTRL_TOG (*(volatile unsigned long *)(REGS_PWM_BASE + 0x0 + 0xc))
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#define BP_PWM_CTRL_SFTRST 31
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#define BM_PWM_CTRL_SFTRST 0x80000000
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#define BF_PWM_CTRL_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BP_PWM_CTRL_CLKGATE 30
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#define BM_PWM_CTRL_CLKGATE 0x40000000
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#define BF_PWM_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BP_PWM_CTRL_PWM4_PRESENT 29
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#define BM_PWM_CTRL_PWM4_PRESENT 0x20000000
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#define BF_PWM_CTRL_PWM4_PRESENT(v) (((v) << 29) & 0x20000000)
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#define BP_PWM_CTRL_PWM3_PRESENT 28
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#define BM_PWM_CTRL_PWM3_PRESENT 0x10000000
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#define BF_PWM_CTRL_PWM3_PRESENT(v) (((v) << 28) & 0x10000000)
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#define BP_PWM_CTRL_PWM2_PRESENT 27
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#define BM_PWM_CTRL_PWM2_PRESENT 0x8000000
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#define BF_PWM_CTRL_PWM2_PRESENT(v) (((v) << 27) & 0x8000000)
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#define BP_PWM_CTRL_PWM1_PRESENT 26
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#define BM_PWM_CTRL_PWM1_PRESENT 0x4000000
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#define BF_PWM_CTRL_PWM1_PRESENT(v) (((v) << 26) & 0x4000000)
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#define BP_PWM_CTRL_PWM0_PRESENT 25
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#define BM_PWM_CTRL_PWM0_PRESENT 0x2000000
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#define BF_PWM_CTRL_PWM0_PRESENT(v) (((v) << 25) & 0x2000000)
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#define BP_PWM_CTRL_PWM4_ENABLE 4
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#define BM_PWM_CTRL_PWM4_ENABLE 0x10
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#define BF_PWM_CTRL_PWM4_ENABLE(v) (((v) << 4) & 0x10)
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#define BP_PWM_CTRL_PWM3_ENABLE 3
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#define BM_PWM_CTRL_PWM3_ENABLE 0x8
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#define BF_PWM_CTRL_PWM3_ENABLE(v) (((v) << 3) & 0x8)
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#define BP_PWM_CTRL_PWM2_ENABLE 2
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#define BM_PWM_CTRL_PWM2_ENABLE 0x4
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#define BF_PWM_CTRL_PWM2_ENABLE(v) (((v) << 2) & 0x4)
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#define BP_PWM_CTRL_PWM1_ENABLE 1
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#define BM_PWM_CTRL_PWM1_ENABLE 0x2
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#define BF_PWM_CTRL_PWM1_ENABLE(v) (((v) << 1) & 0x2)
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#define BP_PWM_CTRL_PWM0_ENABLE 0
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#define BM_PWM_CTRL_PWM0_ENABLE 0x1
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#define BF_PWM_CTRL_PWM0_ENABLE(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_PWM_ACTIVEn
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* Address: 0x10+n*0x20
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* SCT: yes
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*/
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#define HW_PWM_ACTIVEn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x0))
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#define HW_PWM_ACTIVEn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x4))
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#define HW_PWM_ACTIVEn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0x8))
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#define HW_PWM_ACTIVEn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x10+(n)*0x20 + 0xc))
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#define BP_PWM_ACTIVEn_INACTIVE 16
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#define BM_PWM_ACTIVEn_INACTIVE 0xffff0000
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#define BF_PWM_ACTIVEn_INACTIVE(v) (((v) << 16) & 0xffff0000)
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#define BP_PWM_ACTIVEn_ACTIVE 0
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#define BM_PWM_ACTIVEn_ACTIVE 0xffff
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#define BF_PWM_ACTIVEn_ACTIVE(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_PWM_PERIODn
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* Address: 0x20+n*0x20
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* SCT: yes
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*/
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#define HW_PWM_PERIODn(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x0))
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#define HW_PWM_PERIODn_SET(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x4))
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#define HW_PWM_PERIODn_CLR(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0x8))
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#define HW_PWM_PERIODn_TOG(n) (*(volatile unsigned long *)(REGS_PWM_BASE + 0x20+(n)*0x20 + 0xc))
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#define BP_PWM_PERIODn_MATT 23
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#define BM_PWM_PERIODn_MATT 0x800000
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#define BF_PWM_PERIODn_MATT(v) (((v) << 23) & 0x800000)
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#define BP_PWM_PERIODn_CDIV 20
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#define BM_PWM_PERIODn_CDIV 0x700000
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#define BV_PWM_PERIODn_CDIV__DIV_1 0x0
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#define BV_PWM_PERIODn_CDIV__DIV_2 0x1
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#define BV_PWM_PERIODn_CDIV__DIV_4 0x2
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#define BV_PWM_PERIODn_CDIV__DIV_8 0x3
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#define BV_PWM_PERIODn_CDIV__DIV_16 0x4
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#define BV_PWM_PERIODn_CDIV__DIV_64 0x5
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#define BV_PWM_PERIODn_CDIV__DIV_256 0x6
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#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7
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#define BF_PWM_PERIODn_CDIV(v) (((v) << 20) & 0x700000)
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#define BF_PWM_PERIODn_CDIV_V(v) ((BV_PWM_PERIODn_CDIV__##v << 20) & 0x700000)
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#define BP_PWM_PERIODn_INACTIVE_STATE 18
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#define BM_PWM_PERIODn_INACTIVE_STATE 0xc0000
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#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
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#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2
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#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3
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#define BF_PWM_PERIODn_INACTIVE_STATE(v) (((v) << 18) & 0xc0000)
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#define BF_PWM_PERIODn_INACTIVE_STATE_V(v) ((BV_PWM_PERIODn_INACTIVE_STATE__##v << 18) & 0xc0000)
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#define BP_PWM_PERIODn_ACTIVE_STATE 16
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#define BM_PWM_PERIODn_ACTIVE_STATE 0x30000
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#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0
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#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2
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#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3
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#define BF_PWM_PERIODn_ACTIVE_STATE(v) (((v) << 16) & 0x30000)
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#define BF_PWM_PERIODn_ACTIVE_STATE_V(v) ((BV_PWM_PERIODn_ACTIVE_STATE__##v << 16) & 0x30000)
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#define BP_PWM_PERIODn_PERIOD 0
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#define BM_PWM_PERIODn_PERIOD 0xffff
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#define BF_PWM_PERIODn_PERIOD(v) (((v) << 0) & 0xffff)
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#endif /* __HEADERGEN__STMP3600__PWM__H__ */
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