372 lines
20 KiB
C
372 lines
20 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 2.1.7
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* XML versions: stmp3600:2.3.0
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN__STMP3600__GPMI__H__
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#define __HEADERGEN__STMP3600__GPMI__H__
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#define REGS_GPMI_BASE (0x8000c000)
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#define REGS_GPMI_VERSION "2.3.0"
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/**
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* Register: HW_GPMI_CTRL0
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* Address: 0
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* SCT: yes
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*/
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#define HW_GPMI_CTRL0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x0))
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#define HW_GPMI_CTRL0_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x4))
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#define HW_GPMI_CTRL0_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0x8))
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#define HW_GPMI_CTRL0_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x0 + 0xc))
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#define BP_GPMI_CTRL0_SFTRST 31
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#define BM_GPMI_CTRL0_SFTRST 0x80000000
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#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
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#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
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#define BF_GPMI_CTRL0_SFTRST(v) (((v) << 31) & 0x80000000)
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#define BF_GPMI_CTRL0_SFTRST_V(v) ((BV_GPMI_CTRL0_SFTRST__##v << 31) & 0x80000000)
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#define BP_GPMI_CTRL0_CLKGATE 30
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#define BM_GPMI_CTRL0_CLKGATE 0x40000000
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#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
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#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
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#define BF_GPMI_CTRL0_CLKGATE(v) (((v) << 30) & 0x40000000)
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#define BF_GPMI_CTRL0_CLKGATE_V(v) ((BV_GPMI_CTRL0_CLKGATE__##v << 30) & 0x40000000)
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#define BP_GPMI_CTRL0_RUN 29
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#define BM_GPMI_CTRL0_RUN 0x20000000
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#define BV_GPMI_CTRL0_RUN__IDLE 0x0
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#define BV_GPMI_CTRL0_RUN__BUSY 0x1
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#define BF_GPMI_CTRL0_RUN(v) (((v) << 29) & 0x20000000)
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#define BF_GPMI_CTRL0_RUN_V(v) ((BV_GPMI_CTRL0_RUN__##v << 29) & 0x20000000)
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#define BP_GPMI_CTRL0_DEV_IRQ_EN 28
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#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
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#define BF_GPMI_CTRL0_DEV_IRQ_EN(v) (((v) << 28) & 0x10000000)
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#define BP_GPMI_CTRL0_TIMEOUT_IRQ_EN 27
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#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x8000000
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#define BF_GPMI_CTRL0_TIMEOUT_IRQ_EN(v) (((v) << 27) & 0x8000000)
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#define BP_GPMI_CTRL0_UDMA 26
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#define BM_GPMI_CTRL0_UDMA 0x4000000
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#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
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#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
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#define BF_GPMI_CTRL0_UDMA(v) (((v) << 26) & 0x4000000)
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#define BF_GPMI_CTRL0_UDMA_V(v) ((BV_GPMI_CTRL0_UDMA__##v << 26) & 0x4000000)
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#define BP_GPMI_CTRL0_COMMAND_MODE 24
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#define BM_GPMI_CTRL0_COMMAND_MODE 0x3000000
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#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
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#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
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#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
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#define BF_GPMI_CTRL0_COMMAND_MODE(v) (((v) << 24) & 0x3000000)
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#define BF_GPMI_CTRL0_COMMAND_MODE_V(v) ((BV_GPMI_CTRL0_COMMAND_MODE__##v << 24) & 0x3000000)
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#define BP_GPMI_CTRL0_WORD_LENGTH 23
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#define BM_GPMI_CTRL0_WORD_LENGTH 0x800000
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#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
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#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
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#define BF_GPMI_CTRL0_WORD_LENGTH(v) (((v) << 23) & 0x800000)
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#define BF_GPMI_CTRL0_WORD_LENGTH_V(v) ((BV_GPMI_CTRL0_WORD_LENGTH__##v << 23) & 0x800000)
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#define BP_GPMI_CTRL0_LOCK_CS 22
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#define BM_GPMI_CTRL0_LOCK_CS 0x400000
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#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
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#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
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#define BF_GPMI_CTRL0_LOCK_CS(v) (((v) << 22) & 0x400000)
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#define BF_GPMI_CTRL0_LOCK_CS_V(v) ((BV_GPMI_CTRL0_LOCK_CS__##v << 22) & 0x400000)
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#define BP_GPMI_CTRL0_CS 20
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#define BM_GPMI_CTRL0_CS 0x300000
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#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & 0x300000)
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#define BP_GPMI_CTRL0_ADDRESS 17
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#define BM_GPMI_CTRL0_ADDRESS 0xe0000
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#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
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#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
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#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
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#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & 0xe0000)
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#define BF_GPMI_CTRL0_ADDRESS_V(v) ((BV_GPMI_CTRL0_ADDRESS__##v << 17) & 0xe0000)
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#define BP_GPMI_CTRL0_ADDRESS_INCREMENT 16
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#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x10000
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#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
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#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
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#define BF_GPMI_CTRL0_ADDRESS_INCREMENT(v) (((v) << 16) & 0x10000)
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#define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) ((BV_GPMI_CTRL0_ADDRESS_INCREMENT__##v << 16) & 0x10000)
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#define BP_GPMI_CTRL0_XFER_COUNT 0
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#define BM_GPMI_CTRL0_XFER_COUNT 0xffff
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#define BF_GPMI_CTRL0_XFER_COUNT(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_GPMI_COMPARE
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* Address: 0x10
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* SCT: no
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*/
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#define HW_GPMI_COMPARE (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x10))
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#define BP_GPMI_COMPARE_MASK 16
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#define BM_GPMI_COMPARE_MASK 0xffff0000
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#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & 0xffff0000)
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#define BP_GPMI_COMPARE_REFERENCE 0
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#define BM_GPMI_COMPARE_REFERENCE 0xffff
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#define BF_GPMI_COMPARE_REFERENCE(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_GPMI_CTRL1
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* Address: 0x20
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* SCT: yes
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*/
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#define HW_GPMI_CTRL1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x0))
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#define HW_GPMI_CTRL1_SET (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x4))
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#define HW_GPMI_CTRL1_CLR (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0x8))
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#define HW_GPMI_CTRL1_TOG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x20 + 0xc))
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#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
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#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x3000
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#define BF_GPMI_CTRL1_DSAMPLE_TIME(v) (((v) << 12) & 0x3000)
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#define BP_GPMI_CTRL1_DEV_IRQ 10
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#define BM_GPMI_CTRL1_DEV_IRQ 0x400
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#define BF_GPMI_CTRL1_DEV_IRQ(v) (((v) << 10) & 0x400)
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#define BP_GPMI_CTRL1_TIMEOUT_IRQ 9
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#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x200
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#define BF_GPMI_CTRL1_TIMEOUT_IRQ(v) (((v) << 9) & 0x200)
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#define BP_GPMI_CTRL1_BURST_EN 8
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#define BM_GPMI_CTRL1_BURST_EN 0x100
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#define BF_GPMI_CTRL1_BURST_EN(v) (((v) << 8) & 0x100)
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#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 7
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#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x80
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#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY3(v) (((v) << 7) & 0x80)
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#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 6
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#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x40
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#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY2(v) (((v) << 6) & 0x40)
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#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 5
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#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x20
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#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY1(v) (((v) << 5) & 0x20)
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#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 4
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#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x10
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#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY0(v) (((v) << 4) & 0x10)
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#define BP_GPMI_CTRL1_DEV_RESET 3
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#define BM_GPMI_CTRL1_DEV_RESET 0x8
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#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
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#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
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#define BF_GPMI_CTRL1_DEV_RESET(v) (((v) << 3) & 0x8)
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#define BF_GPMI_CTRL1_DEV_RESET_V(v) ((BV_GPMI_CTRL1_DEV_RESET__##v << 3) & 0x8)
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#define BP_GPMI_CTRL1_ATA_IRQRDY_POLARITY 2
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#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x4
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#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
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#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
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#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY(v) (((v) << 2) & 0x4)
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#define BF_GPMI_CTRL1_ATA_IRQRDY_POLARITY_V(v) ((BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__##v << 2) & 0x4)
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#define BP_GPMI_CTRL1_CAMERA_MODE 1
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#define BM_GPMI_CTRL1_CAMERA_MODE 0x2
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#define BF_GPMI_CTRL1_CAMERA_MODE(v) (((v) << 1) & 0x2)
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#define BP_GPMI_CTRL1_GPMI_MODE 0
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#define BM_GPMI_CTRL1_GPMI_MODE 0x1
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#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
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#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
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#define BF_GPMI_CTRL1_GPMI_MODE(v) (((v) << 0) & 0x1)
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#define BF_GPMI_CTRL1_GPMI_MODE_V(v) ((BV_GPMI_CTRL1_GPMI_MODE__##v << 0) & 0x1)
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/**
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* Register: HW_GPMI_TIMING0
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* Address: 0x30
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* SCT: no
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*/
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#define HW_GPMI_TIMING0 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x30))
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#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
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#define BM_GPMI_TIMING0_ADDRESS_SETUP 0xff0000
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#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) (((v) << 16) & 0xff0000)
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#define BP_GPMI_TIMING0_DATA_HOLD 8
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#define BM_GPMI_TIMING0_DATA_HOLD 0xff00
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#define BF_GPMI_TIMING0_DATA_HOLD(v) (((v) << 8) & 0xff00)
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#define BP_GPMI_TIMING0_DATA_SETUP 0
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#define BM_GPMI_TIMING0_DATA_SETUP 0xff
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#define BF_GPMI_TIMING0_DATA_SETUP(v) (((v) << 0) & 0xff)
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/**
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* Register: HW_GPMI_TIMING1
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* Address: 0x40
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* SCT: no
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*/
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#define HW_GPMI_TIMING1 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x40))
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#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
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#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xffff0000
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#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) (((v) << 16) & 0xffff0000)
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#define BP_GPMI_TIMING1_ATA_READY_TIMEOUT 0
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#define BM_GPMI_TIMING1_ATA_READY_TIMEOUT 0xffff
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#define BF_GPMI_TIMING1_ATA_READY_TIMEOUT(v) (((v) << 0) & 0xffff)
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/**
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* Register: HW_GPMI_TIMING2
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* Address: 0x50
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* SCT: no
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*/
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#define HW_GPMI_TIMING2 (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x50))
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#define BP_GPMI_TIMING2_UDMA_TRP 24
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#define BM_GPMI_TIMING2_UDMA_TRP 0xff000000
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#define BF_GPMI_TIMING2_UDMA_TRP(v) (((v) << 24) & 0xff000000)
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#define BP_GPMI_TIMING2_UDMA_ENV 16
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#define BM_GPMI_TIMING2_UDMA_ENV 0xff0000
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#define BF_GPMI_TIMING2_UDMA_ENV(v) (((v) << 16) & 0xff0000)
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#define BP_GPMI_TIMING2_UDMA_HOLD 8
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#define BM_GPMI_TIMING2_UDMA_HOLD 0xff00
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#define BF_GPMI_TIMING2_UDMA_HOLD(v) (((v) << 8) & 0xff00)
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#define BP_GPMI_TIMING2_UDMA_SETUP 0
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#define BM_GPMI_TIMING2_UDMA_SETUP 0xff
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#define BF_GPMI_TIMING2_UDMA_SETUP(v) (((v) << 0) & 0xff)
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/**
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* Register: HW_GPMI_DATA
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* Address: 0x60
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* SCT: no
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*/
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#define HW_GPMI_DATA (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x60))
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#define BP_GPMI_DATA_DATA 0
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#define BM_GPMI_DATA_DATA 0xffffffff
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#define BF_GPMI_DATA_DATA(v) (((v) << 0) & 0xffffffff)
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/**
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* Register: HW_GPMI_STAT
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* Address: 0x70
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* SCT: no
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*/
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#define HW_GPMI_STAT (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x70))
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#define BP_GPMI_STAT_PRESENT 31
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#define BM_GPMI_STAT_PRESENT 0x80000000
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#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
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#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
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#define BF_GPMI_STAT_PRESENT(v) (((v) << 31) & 0x80000000)
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#define BF_GPMI_STAT_PRESENT_V(v) ((BV_GPMI_STAT_PRESENT__##v << 31) & 0x80000000)
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#define BP_GPMI_STAT_RDY_TIMEOUT 8
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#define BM_GPMI_STAT_RDY_TIMEOUT 0xf00
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#define BF_GPMI_STAT_RDY_TIMEOUT(v) (((v) << 8) & 0xf00)
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#define BP_GPMI_STAT_ATA_IRQ 7
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#define BM_GPMI_STAT_ATA_IRQ 0x80
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#define BF_GPMI_STAT_ATA_IRQ(v) (((v) << 7) & 0x80)
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#define BP_GPMI_STAT_FIFO_EMPTY 5
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#define BM_GPMI_STAT_FIFO_EMPTY 0x20
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#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
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#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
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#define BF_GPMI_STAT_FIFO_EMPTY(v) (((v) << 5) & 0x20)
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#define BF_GPMI_STAT_FIFO_EMPTY_V(v) ((BV_GPMI_STAT_FIFO_EMPTY__##v << 5) & 0x20)
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#define BP_GPMI_STAT_FIFO_FULL 4
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#define BM_GPMI_STAT_FIFO_FULL 0x10
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#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
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#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
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#define BF_GPMI_STAT_FIFO_FULL(v) (((v) << 4) & 0x10)
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#define BF_GPMI_STAT_FIFO_FULL_V(v) ((BV_GPMI_STAT_FIFO_FULL__##v << 4) & 0x10)
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#define BP_GPMI_STAT_DEV3_ERROR 3
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#define BM_GPMI_STAT_DEV3_ERROR 0x8
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#define BF_GPMI_STAT_DEV3_ERROR(v) (((v) << 3) & 0x8)
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#define BP_GPMI_STAT_DEV2_ERROR 2
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#define BM_GPMI_STAT_DEV2_ERROR 0x4
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#define BF_GPMI_STAT_DEV2_ERROR(v) (((v) << 2) & 0x4)
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#define BP_GPMI_STAT_DEV1_ERROR 1
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#define BM_GPMI_STAT_DEV1_ERROR 0x2
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#define BF_GPMI_STAT_DEV1_ERROR(v) (((v) << 1) & 0x2)
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#define BP_GPMI_STAT_DEV0_ERROR 0
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#define BM_GPMI_STAT_DEV0_ERROR 0x1
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#define BF_GPMI_STAT_DEV0_ERROR(v) (((v) << 0) & 0x1)
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/**
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* Register: HW_GPMI_DEBUG
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* Address: 0x80
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* SCT: no
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*/
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#define HW_GPMI_DEBUG (*(volatile unsigned long *)(REGS_GPMI_BASE + 0x80))
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#define BP_GPMI_DEBUG_READY3 31
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#define BM_GPMI_DEBUG_READY3 0x80000000
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#define BF_GPMI_DEBUG_READY3(v) (((v) << 31) & 0x80000000)
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#define BP_GPMI_DEBUG_READY2 30
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#define BM_GPMI_DEBUG_READY2 0x40000000
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#define BF_GPMI_DEBUG_READY2(v) (((v) << 30) & 0x40000000)
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#define BP_GPMI_DEBUG_READY1 29
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#define BM_GPMI_DEBUG_READY1 0x20000000
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#define BF_GPMI_DEBUG_READY1(v) (((v) << 29) & 0x20000000)
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#define BP_GPMI_DEBUG_READY0 28
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#define BM_GPMI_DEBUG_READY0 0x10000000
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#define BF_GPMI_DEBUG_READY0(v) (((v) << 28) & 0x10000000)
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#define BP_GPMI_DEBUG_WAIT_FOR_READY_END3 27
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#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x8000000
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#define BF_GPMI_DEBUG_WAIT_FOR_READY_END3(v) (((v) << 27) & 0x8000000)
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#define BP_GPMI_DEBUG_WAIT_FOR_READY_END2 26
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#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x4000000
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#define BF_GPMI_DEBUG_WAIT_FOR_READY_END2(v) (((v) << 26) & 0x4000000)
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#define BP_GPMI_DEBUG_WAIT_FOR_READY_END1 25
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#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x2000000
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#define BF_GPMI_DEBUG_WAIT_FOR_READY_END1(v) (((v) << 25) & 0x2000000)
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#define BP_GPMI_DEBUG_WAIT_FOR_READY_END0 24
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#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x1000000
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#define BF_GPMI_DEBUG_WAIT_FOR_READY_END0(v) (((v) << 24) & 0x1000000)
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#define BP_GPMI_DEBUG_SENSE3 23
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#define BM_GPMI_DEBUG_SENSE3 0x800000
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#define BF_GPMI_DEBUG_SENSE3(v) (((v) << 23) & 0x800000)
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#define BP_GPMI_DEBUG_SENSE2 22
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#define BM_GPMI_DEBUG_SENSE2 0x400000
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#define BF_GPMI_DEBUG_SENSE2(v) (((v) << 22) & 0x400000)
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#define BP_GPMI_DEBUG_SENSE1 21
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#define BM_GPMI_DEBUG_SENSE1 0x200000
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#define BF_GPMI_DEBUG_SENSE1(v) (((v) << 21) & 0x200000)
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#define BP_GPMI_DEBUG_SENSE0 20
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#define BM_GPMI_DEBUG_SENSE0 0x100000
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#define BF_GPMI_DEBUG_SENSE0(v) (((v) << 20) & 0x100000)
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#define BP_GPMI_DEBUG_DMAREQ3 19
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#define BM_GPMI_DEBUG_DMAREQ3 0x80000
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#define BF_GPMI_DEBUG_DMAREQ3(v) (((v) << 19) & 0x80000)
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#define BP_GPMI_DEBUG_DMAREQ2 18
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#define BM_GPMI_DEBUG_DMAREQ2 0x40000
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#define BF_GPMI_DEBUG_DMAREQ2(v) (((v) << 18) & 0x40000)
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#define BP_GPMI_DEBUG_DMAREQ1 17
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#define BM_GPMI_DEBUG_DMAREQ1 0x20000
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#define BF_GPMI_DEBUG_DMAREQ1(v) (((v) << 17) & 0x20000)
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#define BP_GPMI_DEBUG_DMAREQ0 16
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#define BM_GPMI_DEBUG_DMAREQ0 0x10000
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#define BF_GPMI_DEBUG_DMAREQ0(v) (((v) << 16) & 0x10000)
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#define BP_GPMI_DEBUG_CMD_END 12
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#define BM_GPMI_DEBUG_CMD_END 0xf000
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#define BF_GPMI_DEBUG_CMD_END(v) (((v) << 12) & 0xf000)
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#define BP_GPMI_DEBUG_UDMA_STATE 8
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#define BM_GPMI_DEBUG_UDMA_STATE 0xf00
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#define BF_GPMI_DEBUG_UDMA_STATE(v) (((v) << 8) & 0xf00)
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#define BP_GPMI_DEBUG_BUSY 7
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#define BM_GPMI_DEBUG_BUSY 0x80
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#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
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#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1
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#define BF_GPMI_DEBUG_BUSY(v) (((v) << 7) & 0x80)
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#define BF_GPMI_DEBUG_BUSY_V(v) ((BV_GPMI_DEBUG_BUSY__##v << 7) & 0x80)
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#define BP_GPMI_DEBUG_PIN_STATE 4
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#define BM_GPMI_DEBUG_PIN_STATE 0x70
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
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#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
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#define BF_GPMI_DEBUG_PIN_STATE(v) (((v) << 4) & 0x70)
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#define BF_GPMI_DEBUG_PIN_STATE_V(v) ((BV_GPMI_DEBUG_PIN_STATE__##v << 4) & 0x70)
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#define BP_GPMI_DEBUG_MAIN_STATE 0
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#define BM_GPMI_DEBUG_MAIN_STATE 0xf
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
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#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xa
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#define BF_GPMI_DEBUG_MAIN_STATE(v) (((v) << 0) & 0xf)
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#define BF_GPMI_DEBUG_MAIN_STATE_V(v) ((BV_GPMI_DEBUG_MAIN_STATE__##v << 0) & 0xf)
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#endif /* __HEADERGEN__STMP3600__GPMI__H__ */
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