0b6198f8a8
The current driver only works in PIO mode. Change-Id: I1cf2eaedcce0172a254c3bab0e1257886226d3a0
232 lines
7.1 KiB
C
232 lines
7.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2013 Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef ATA_IMX233_H
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#define ATA_IMX233_H
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#include "config.h"
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#include "system.h"
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#include "pinctrl-imx233.h"
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#include "clkctrl-imx233.h"
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#include "ata-target.h"
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#include "ata-defines.h"
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#include "regs/regs-gpmi.h"
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struct pio_timing_t
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{
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/** all values are in ns */
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int addr_setup; /* "Address valid to DIOR-/DIOW-setup" */
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int data_hold; /* "DIOR-/DIOW-recovery time" */
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int data_setup; /* "DIOR-/DIOW-" */
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};
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static struct pio_timing_t pio_timing[] =
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{
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/* FIXME: OF uses 290, 290, 290, 80, 70 for data_setup */
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{70, 100, 165},
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{50, 100, 125},
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{30, 100, 100},
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{30, 70, 80},
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{25, 25, 70},
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};
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static void imx233_ata_wait_ready(void)
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{
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while(BF_RD(GPMI_CTRL0, RUN))
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yield();
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}
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static uint16_t imx233_ata_read_reg(unsigned reg)
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{
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/* wait ready */
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imx233_ata_wait_ready();
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/* setup command */
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HW_GPMI_CTRL0 = BF_OR6(GPMI_CTRL0, RUN(1),
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COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ),
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WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__16_BIT),
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CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)),
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XFER_COUNT(1));
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/* wait for completion */
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while(BF_RD(GPMI_STAT, FIFO_EMPTY));
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/* get data */
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return HW_GPMI_DATA & 0xffff;
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}
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static void imx233_ata_write_reg(unsigned reg, uint16_t data)
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{
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/* wait ready */
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imx233_ata_wait_ready();
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/* setup command */
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HW_GPMI_CTRL0 = BF_OR6(GPMI_CTRL0, RUN(1),
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COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE),
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WORD_LENGTH(BV_GPMI_CTRL0_WORD_LENGTH__16_BIT),
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CS(IMX233_ATA_REG_CS(reg)), ADDRESS(IMX233_ATA_REG_ADDR(reg)),
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XFER_COUNT(1));
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/* send data */
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HW_GPMI_DATA = data;
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}
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uint8_t imx233_ata_inb(unsigned reg)
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{
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return imx233_ata_read_reg(reg) & 0xff;
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}
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uint16_t imx233_ata_inw(unsigned reg)
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{
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return imx233_ata_read_reg(reg);
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}
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void imx233_ata_outb(unsigned reg, uint8_t v)
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{
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imx233_ata_write_reg(reg, v);
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}
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void imx233_ata_outw(unsigned reg, uint16_t v)
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{
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imx233_ata_write_reg(reg, v);
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}
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void ata_set_pio_timings(int mode)
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{
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/* load timing */
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struct pio_timing_t t = pio_timing[mode > 3 ? 3 : mode];
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/* adjust to the clock */
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unsigned clock_freq = 80 * 1000;
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#define adjust_to_clock(val) \
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val = (val * clock_freq) / 1000 / 1000
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adjust_to_clock(t.addr_setup);
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adjust_to_clock(t.data_hold);
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adjust_to_clock(t.data_setup);
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/* write */
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imx233_ata_wait_ready();
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HW_GPMI_TIMING0 = BF_OR3(GPMI_TIMING0, ADDRESS_SETUP(t.addr_setup),
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DATA_HOLD(t.data_hold), DATA_SETUP(t.data_setup));
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}
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void ata_reset(void)
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{
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/* reset device */
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BF_WR_V(GPMI_CTRL1, DEV_RESET, ENABLED);
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sleep(HZ / 10);
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BF_WR_V(GPMI_CTRL1, DEV_RESET, DISABLED);
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}
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void ata_enable(bool on)
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{
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}
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bool ata_is_coldstart(void)
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{
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return false;
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}
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#ifdef HAVE_ATA_DMA
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void ata_dma_set_mode(unsigned char mode);
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bool ata_dma_setup(void *addr, unsigned long bytes, bool write);
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bool ata_dma_finish(void);
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#endif
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static int ata_wait_status(unsigned status, unsigned mask, int timeout)
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{
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long end_tick = current_tick + timeout;
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while(TIME_BEFORE(current_tick, end_tick))
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{
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if((ATA_IN8(ATA_STATUS) & mask) == status)
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return 1;
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sleep(0);
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}
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return 0;
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}
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int ata_wait_for_bsy(void)
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{
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/* BSY = 0 */
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return ata_wait_status(0, STATUS_BSY, HZ);
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}
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int ata_wait_for_rdy(void)
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{
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/* RDY = 1 && BSY = 0 */
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return ata_wait_status(STATUS_RDY, STATUS_RDY | STATUS_BSY, HZ);
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}
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void ata_device_init(void)
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{
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/* reset block */
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imx233_reset_block(&HW_GPMI_CTRL0);
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/* setup pins */
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D0, "ata d0", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D1, "ata d1", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D2, "ata d2", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D3, "ata d3", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D4, "ata d4", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D5, "ata d5", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D6, "ata d6", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D7, "ata d7", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D8, "ata d8", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D9, "ata d9", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D10, "ata d10", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D11, "ata d11", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D12, "ata d12", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D13, "ata d13", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D14, "ata d14", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D15, "ata d15", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_D15, "ata d15", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_CE0n, "ata cs0", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_CE1n, "ata cs1", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_A0, "ata a0", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_A1, "ata a1", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_A2, "ata a2", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_IRQ, "ata irq", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_RDY, "ata rdy", PINCTRL_DRIVE_4mA, false);
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#ifdef HAVE_ATA_DMA
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imx233_pinctrl_setup_vpin(VPIN_GPMI_RDY2, "ata dmack", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_RDY3, "ata dmarq", PINCTRL_DRIVE_4mA, false);
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#endif
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imx233_pinctrl_setup_vpin(VPIN_GPMI_RDn, "ata rd", PINCTRL_DRIVE_4mA, false);
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imx233_pinctrl_setup_vpin(VPIN_GPMI_WRn, "ata wr", PINCTRL_DRIVE_4mA, false);
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/* setup ata mode */
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BF_WR_V(GPMI_CTRL1, GPMI_MODE, ATA);
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/* reset device */
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ata_reset();
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ata_enable(true);
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/* setup mode 0 for all until identification */
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ata_set_pio_timings(0);
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#ifdef HAVE_ATA_DMA
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ata_set_mdma_timings(0);
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ata_set_udma_timings(0);
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#endif
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}
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#endif /* ATA_IMX233_H */
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